Apple II Communications Card

The Apple II Communications Card was one of the very first interface cards from Apple, dating to 1978. It uses a 6850 UART and is intended to communicate with other computers using a (most likely acoustically coupled) modem over the telephone lines at 110 or 300 Baud (or bits per second).

The Communications Card did not support any hardware handshaking, limiting its use.

You can download the manual from

The schematic is available from the Apple II Documentation Project> Ignore the photo they have up there, that's a much different beast.

Schematic from the documentation project

Most of the schematic is fairly standard -- a ROM, a buffer and some chip-select transistors -- very similar to the parallel or FDC interfaces.

The clock generator, however, is... strange.

Clock Divider from Schematic

A flip-flop like the 74LS74 above will generally clock data on the D pin into its register when it receives a clock pulse on C. S and R are used to set and reset the outputs. Q is the data once clocked in, and /Q is just Q, inverted.

But in this case, both clock and data are tied low. Off to the datasheet.

Function Table from TI datasheet

Turns out that once you tie the clear input low, the clock and data inputs don't matter any more. Q becomes the opposite of the set input, and /Q is always high.

OK, so I get it. Half the flip-flop is used as an inverter. This is 100% in the spirit of Woz. Use what you have available, don't go adding a chip to use one inverter, i.e. 1/6 of the package, while leaving half of another chip you could have used instead, unused.

So why route /Q, which is always high, to the two '161s? I have no idea. The only reason I can think of is to save a pull-up resistor. It used to be, before LS, that TTL best practice was to never tie a gate high directly but to always use a pull-up or "Soft 5" (see for example 74LS00 at location A2 on the motherboard (close to the video output connector on the schematic)). This limits inrush current on power-up, and became an obsolete practice with 74LS parts and is not at all necessary with CMOS parts, which the '161s are. But I guess old habits die hard. Especially if they show how clever you are abusing a flip-flop in a Wozian way.

OK, so now it's easy. The two counters do that, count, from their preset value on P3..P0 up to 0xFF. When A2 reaches 0xFF it carries one to A1, and when A1 reaches 0xFF the carry is inverted and re-loads the preset value (yea, on start-up the first cycle might run from 0 - 0xFF but after that things will settle down).

Depending on the state of /RTS, which is used as a register-controlled output from the UART and not a Request-to-Send line (no handshaking support, remember), the counters start from either 2B or 6F,dividing by 213 and 145 respectively. But wait! There's more! The 6850 UART can divide the input clock by 64, 16, or 1. Division by one is useless in this case, it's only used in synchronous applications. For 300 baud, divide-by-16 is used and for 110 baud, divide-by-64.

Had I built this board I would maybe have made the first ratio something like 53, to give me 300 baud with the UART at divide-by-64 and 1200 baud with the UART set to divide-by-16. But maybe they figured the error would be too high (1206 and 302 baud).

Edit-to-Add: On the second board I have, /RTS is disconnected from the two '161s, and the preset value is 0xCB, i.e. divide-by-53. Also, Q1 is used as the output instead of Q3, this gives a closer-to-50% ratio -- not that it matters if it gets divided by another 16 or 64, but hey.

With the right divisors, this board will do 2400 baud (1.3% error) but at 4800 baud the error is 2.5% which is starting to push things. Faster than that, you're on your own.

Oh yes and what about the other half of the 74LS74? It latches the /RESET signal until the first time you read the UART. I suppose this might be useful information, dunno.

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