The Cape Computer Club 6809 Microsystem

I inherited my friend Barney de Villiers' 6809 Microsystem. Here is where I keep everything I know about it.

The 6809 Microsystem - Specifications by Jonathan Eva and Neil Walsh.

6809 Microsystem System Software -- 4k debug / monitor EPROM.

The PCBs

Processor Board

Barney never bothered to cover the EPROM window. But the data is still fine (6809-MSS.BIN).

RAM Board

Note the very neat modification to connect /IOS to the address decoders using the WAIT pin which is not used by the RAM board. See the 6809 Microsystem Specification for more information.

CRTC

Kind of boring. Unlike the Apple ][ 80 column card, which has four 2114 chips for 2 kilobytes of screen memory (enough for 80 columns x 24 rows = 1920 bytes) and one or two 2716 2 kilobyte EPROMs to hold the actual character maps, this CRTC has two banks of 4 kilobyte RAM, one for the screen memory and one for the character maps, which has to be written to the RAM by the processor on startup. This of course allows for special characters / graphics.

CRT Controller

Serial I/O

Two 6850s and an Intel(!) 8253 timer instead of the more conventional-in-Motorola-world 6840.

Parallel I/O

This provides a keyboard interface and a Real-Time Clock (under the ribbon cable). The batteries were flat but not leaking (this is a Good Thing).

Floppy Disk Controller

One of the later boards added to the stable, it also incorporates the I/O page decoding from the 18-bit physical address space.

The PCB itself precedes the schematic -- look closely at U21, there are no pads on the PCB for it -- obviously a later addition. It seems to match the schematic though. I would have dead-bugged the mod but I have to say, this way is ridiculously professional.

Schematics in PDF format

Dynamic Address Translation

DAT is a way of mapping the 16-bit (64 kilobyte) processor logical address space to a larger (in this specific case 256 kilobyte but easily changed to 1 Megabyte) physical address space in blocks of (in this case) 4 kilobytes.

It gets a bit complex, but basically a static RAM device (DAT RAM) is connected in such a way that the upper (in this case) 4 logical address lines from the CPU (the logical address lines) provide the address lines to the DAT RAM and the data from the DAT RAM becomes (in this case) 6 (but obviously easily 8) address lines (the physical address lines), and depending on where you start intercepting the logical address lines this defines the block size and the physical memory size.

Specifically: logical A12-A15 provides the address lines to the DAT RAM. The DAT RAM provides physical A12-A15 as well as a newly generated A16 and A17 (and, trivially, A18 and A19 because the DAT RAM is eight bytes wide -- but not in this specific case).

Physical RAM block size is (A0-A11) 4 kilobytes. Logical RAM size is (A0-A17) 256 kilobytes.

The DAT RAM must obviously contain the mapping from the logical to the physical RAM. And more importantly, we need a mechanism to write the mapping to this RAM. In practice, the RAM is mapped to the high end of the physical address space, and provision is made to turn the DAT translation off for that block of memory -- so reads from 0xFFxx are always mapped to 0x3FFxx, and writes to 0xFFxx go into the DAT RAM (with more gates this could be 0xFFFx but there's no sense since a typical system needs at least 256 bytes of ROM -- but if you wanted to you could).

Excerpt from the GIMIX 6809+ CPU BOARD manual.

CRT Display

The CRT Display is a Motorola M68MDM-1 (see page 3-61). A.K.A. M1000. Schematics at Radiomuseum.

It uses a 140ANB4 picture tube.

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