Wozpak ][, November 1979, pages 109-115.
FLOATING POINT PACKAGE
The mantissa-exponent, or 'floating point' numerical representation is
widely used by computers to express values with a wide dynamic range. With
floating point representation, the number 7.5 x 10^22 requires no more
memory to store than the number 75 does. We have allowed for binary
floating point arithmetic on the APPLE ][ computer by providing a useful
subroutine package in ROM, which performs the common arithmetic functions.
Maximum precision is retained by these routines and overflow conditions
such as 'divide by zero' are trapped for the user. The 4-byte floating
point number representation is compatible with future APPLE products such
as floating point BASIC.
A small amount of memory in Page Zero is dedicated to the floating point
workspace, including the two floating-point accumulators, FP1 and FP2.
After placing operands in these accumulators, the user calls subroutines in
the ROM which perform the desired arithmetic operations, leaving results in
FP1. Should an overflow condition occur, a jump to location $3F5 is
executed, allowing a user routine to take appropriate action.
FLOATING POINT REPRESENTATION
_____ _____ _____ _____
| | | | | | | |
| | | HI | | | | LOW |
|_____| |_____| |_____| |_____|
Exponent Signed Mantissa
1. Mantissa
The floating point mantissa is stored in two's complement representation
with the sign at the most significant bit (MSB) position of the high-order
mantissa byte. The mantissa provides 24 bits of precision, including sign,
and can represent 24-bit integers precisely. Extending precision is simply
a matter of adding bytes at the low order end of the mantissa.
Except for magnitudes less than 2^-128 (which lose precision) mantissa are
normalized by the floating point routines to retain maximum precision.
That is, the numbers are adjusted so that the upper two high-order mantissa
bits are unequal.
HIGH-ORDER MANTISSA BYTE
01.XXXXXX Positive mantissa.
10.XXXXXX Negative mantissa.
00.XXXXXX Unnormalized mantissa.
11.XXXXXX Exponent = -128.
2. Exponent.
The exponent is a binary scaling factor (power of two) which is applied to
the mantissa. Ranging from -128 to +127, the exponent is stored in
standard two's complement representation except for the sign bit which is
complemented. This representation allows direct comparison of exponents,
since they are stored in increasing numerical sequence. The most negative
exponent, corresponding to the smallest magnItude, -128, is stored as $00
($ means hexidecimal) and the most positive, +127, is stored as $FF (all
ones).
EXPONENT STORED AS
+127 11111111 ($FF)
+3 10000011 ($83)
+2 10000010 ($82)
+1 10000001 ($81)
0 10000000 ($80)
-1 01111111 ($7F)
-2 01111110 ($7E)
-3 01111101 ($7D)
-128 00000000 ($00)
The smallest magnitude which can be represented is 2^-150.
_____ _____ _____ _____
| | | | | | | |
| 0 | | 0 | | 0 | | 1 |
|_____| |_____| |_____| |_____|
HIGH LOW
EXP MANTISSA
The largest positive magnitude which can be represented is +2^128-1.
_____ _____ _____ _____
| | | | | | | |
| $7F | | $7F | | $FF | | $FF |
|_____| |_____| |_____| |_____|
EXP MANTISSA
FLOATING POINT REPRESENTATION EXAMPLES
DECIMAL HEX HEX
NUMBER EXPONENT MANTISSA
+ 3 81 60 00 00
+ 4 82 40 00 00
+ 5 82 50 00 00
+ 7 82 70 00 00
+12 83 60 00 00
+15 83 78 00 00
+17 84 44 00 00
+20 84 50 00 00
+60 85 78 00 00
- 3 81 A0 00 00
- 4 81 80 00 00
- 5 82 B0 00 00
- 7 82 90 00 00
-12 83 A0 00 00
-15 83 88 00 00
-17 84 BC 00 00
-20 84 B0 00 00
-60 85 88 00 00
FLOATING POINT SUBROUTINE DESCRIPTIONS
FCOMPL subroutine (address $F4A4)
Purpose: FCOMPL is used to negate floating point numbers.
Entry: A normalized or unnormalized value is in FP1 (floating point
accumulator 1).
Uses: NORM, RTLOG.
Exit: The value in FP1 is negated and then normalized to retain precision.
The 3-byte FP1 extension, E, may also be altered but FP2 and SIGN are not
disturbed. The 6502 A-REG is altered and the X-REG is cleared. The Y-REG
is not disturbed.
Caution: Attempting to negate -2^128 will result in an overflow since
+2^128 is not representable, and a jump to location $3F5 will be executed,
with the following contents in FP1.
_____ _____ _____ _____
| | | | | | | |
FP1: | 0 | | $80 | | 0 | | 0 |
|_____| |_____| |_____| |_____|
X1 M1
Example: Prior to calling FCOMPL, FP1 contains +15.
_____ _____ _____ _____
| | | | | | | |
FP1: | $83 | | $78 | | 0 | | 0 | (+15)
|_____| |_____| |_____| |_____|
X1 M1
After calling FCOMPL as a subroutine, FP1 contains -15.
_____ _____ _____ _____
| | | | | | | |
FP1: | $83 | | $88 | | 0 | | 0 | (+15)
|_____| |_____| |_____| |_____|
X1 M1
FADD subroutine (address $F46E)
Purpose: To add two numbers in floating point form.
Entry: The two addends are in FP1 and FP2 respectively. For maximum
precision, both should be normalized.
Uses: SWPALGN, ADD, NORM, RTLOG.
Exit: The normalized sum is left in FP1. FP2 contains the addend of
greatest magnitude. E is altered but sign is not. The A-REG is altered
and the X-REG is cleared. The sum mantissa is truncated to 24 bits.
Caution: Overflow may result if the sum is less that -2^128 or greater than
+2^128-1. If so, a jump to location $3F5 is executed leaving 0 in X1, and
twice the proper sum in the mantissa M1. The sign bit is left in the
carry, 0 for positive, 1 for negative.
_____ __________
| | | |
FP1: | 0 | | X.YYY... |
|_____| |__________|
X1 M1
(For carry=0, true sum=+X.YYY x 2^128)
Example: Prior to calling FADD, FP1 contains +12 and FP2 contains -5.
_____ _____ _____ _____
| | | | | | | |
FP1: | $83 | | $60 | | 0 | | 0 | (+12)
|_____| |_____| |_____| |_____|
X1 M1
_____ _____ _____ _____
| | | | | | | |
FP2: | $82 | | $B0 | | 0 | | 0 | (-5)
|_____| |_____| |_____| |_____|
X2 M2
After calling FADD, FP1 contains +7 (FP2 contains +12).
_____ _____ _____ _____
| | | | | | | |
FP1 | $82 | | $70 | | 0 | | 0 | (+7)
|_____| |_____| |_____| |_____|
X1 M1
FSUB subroutine (address $F468)
Purpose: To subtract two floating point numbers.
Entry: The minuend is in FP1 and the subtrahend is in FP2. Both should be
normalized to retain maximum precision prior to calling FSUB.
Uses: FCOMPL, ALGNSWP, FADD, ADD, NORM, RTLOG.
Exit: The normalized difference is in FP1 with the mantissa truncated to 24
bits. FP2 holds either the minued or the negated subtrahend, whichever is
of greater magnitude. E is altered but SIGN and SCR are not. the A-REG is
altered and the X-REG is cleared. The Y-REG is not disturbed.
Cautions: An exit to location S3F5 is taken if the result is less than
-2^128 or greater than +2^128-1. or if the subtrahend is -2^128.
Example: Prior to calling FSUB, FP1 contains +7 (minuend) and FP2 contalns
-5 (subtrahend).
_____ _____ _____ _____
| | | | | | | |
FP1: | $82 | | $70 | | 0 | | 0 | (+12)
|_____| |_____| |_____| |_____|
X1 M1
_____ _____ _____ _____
| | | | | | | |
FP2: | $82 | | $B0 | | 0 | | 0 | (- 5)
|_____| |_____| |_____| |_____|
X2 M2
After calling FSUB, FP1 contains +12 and FP2 contains +7.
_____ _____ _____ _____
| | | | | | | |
FP1: | $83 | | $60 | | 0 | | 0 | (+12)
|_____| |_____| |_____| |_____|
X1 M1
FMUL subroutine (address $F48C)
Purpose: To multiply floating point numbers.
Entry: The multiplicand and multiplier must reside in FP1 and FP2
respectively. Both should be normalized prior to calling FMUL to retain
maximum precision.
Uses: MD1, MD2, RTLOG1, ADD, MDEND.
Exit: The signed normalized floating point product is left in FP1. M1 is
truncated to contain the 24 most significant mantissa bits (including
sign). The absolute value of the multiplier mantissa (M2) is left in FP2.
E, SIGN, and SCR are altered. The A- and X-REGs are altered and the Y-REG
contains $FF upon exit.
Cautions: An exit to location $3F5 is taken if the product is less than
-2^128 or greater than +2^128-1.
Notes: FMUL will run faster if the absolute value of the multiplier
mantissa contains fewer '1's than the absolute value of the multiplicand
mantissa.
Example: Prior to calling FMUL, FP1 contains +12 and FP2 contains -5.
_____ _____ _____ _____
| | | | | | | |
FP1: | $83 | | $60 | | 0 | | 0 | (+12)
|_____| |_____| |_____| |_____|
X1 M1
_____ _____ _____ _____
| | | | | | | |
FP2: | $82 | | $B0 | | 0 | | 0 | (- 5)
|_____| |_____| |_____| |_____|
X2 M2
After calling FMUL, FP1 contains -60 and FP2 contains +5.
_____ _____ _____ _____
| | | | | | | |
FP1: | $85 | | $88 | | 0 | | 0 | (-60)
|_____| |_____| |_____| |_____|
X1 M1
_____ _____ _____ _____
| | | | | | | |
FP2: | $82 | | $50 | | 0 | | 0 | (+ 5)
|_____| |_____| |_____| |_____|
X2 M2
FDIV subroutine (addr $F4B2)
Purpose: To perform division of floating point numbers.
Entry: The normalized dividend is in FP2 and the normalized divisor is in
FP1.
Exit: The signed normalized floating point quotient is left in FP1. The
mantissa (M1) is truncated to 24 bits. The 3-bit M1 extension (E) contains
the absolute value of the divisor mantissa. MD2, SIGN, and SCR are
altered. The A- and X-REGs are altered and the Y-REG is cleared.
Uses: MD1, MD2, MDEND.
Cautions: An exit to location $3F5 is taken if the quotient is less than
-2^128 or greater than +2^128-1
Notes: MD2 contains the remainder mantissa (equivalent to the MOD
function). The remainder exponent is the same as the quotient exponent, or
1 less if the dividend mantissa magnitude is less than the divisor mantissa
magnitude.
Example: Prior to calling FDIV, FP1 contains -60 (dividend), and FP2
contains +12 (divisor).
_____ _____ _____ _____
| | | | | | | |
FP1: | $85 | | $80 | | 0 | | 0 | (-60)
|_____| |_____| |_____| |_____|
X1 M1
_____ _____ _____ _____
| | | | | | | |
FP2 | $83 | | $60 | | 0 | | 0 | (+12)
|_____| |_____| |_____| |_____|
X1 M1
After calling FMUL, FP1 contains -5 and M2 contains 0.
_____ _____ _____ _____
| | | | | | | |
FP1: | $82 | | $B0 | | 0 | | 0 | (-5)
|_____| |_____| |_____| |_____|
X1 M1
FLOAT Subroutine (address $F451)
Purpose: To convert integers to floating point representation.
Entry: A signed (two's complement) 2-byte integer is stored in M1
(high-order byte) and M1+1 (low-order byte). M1+2 must be cleared by user
prior to entry.
Uses: NORM1.
Exit: The normalized floating point equivalent is left in FP1. E, FP2,
SIGN, and SCR are not disturbed. The A-REG contains a copy of the
high-order mantissa byte upon exit but the X- and Y-REGs are not disturbed.
The carry is cleared.
Notes: To float a 1-byte integer, place it in M1+1 and clear M1 as well as
M1+2 prior to calling FLOAT.
FLOAT takes approximately 3 msec. lonqer to convert zero to floating point
form than other arguments. The user may check for zero prior to calling
FLOAT and increase throughput.
*
* LOW-ORDER INT. BYTE IN A-REG
* HIGH-ORDER BYTE IN Y-REG
*
85 FA XFLOAT STA M1+1
84 F9 STY M1 INIT MANT1
A0 00 LDY #$0
84 FB STY M1+2
05 D9 ORA M1 CHK BOTH
BYTES FOR
D0 03 BNE TOFLOAT ZERO
85 F8 STA X1 IF SO CLR X1
60 RTS AND RETURN
4C 51 F4 TOFLOAT JMP FLOAT ELSE FLOAT
INTEGER
Example: Float +274 ($0112 hex)
CALLING SEQUENCE
A0 01 LDY #$01 HIGH-ORDER
INTEGER BYTE
A9 12 LDA #$12 LOW-ORDER
INTEGER BYTE
84 F9 STY M1
85 FA STA M1+1
A9 00 LDA #$00
85 F8 STA M1+2
20 51 F4 JSR FLOAT
Upon returning from FLOAT, FP1 contains the floating point representation
of +274.
_____ _____ _____ _____
| | | | | | | |
FP1 | $88 | | $44 | | $80 | | 0 | (+274)
|_____| |_____| |_____| |_____|
X1 M1
FIX subroutine (address $F640)
Purpose: To extract the integer portion of a floating point number with
truncation (ENTIER function).
Entry: A floating point value is in FP1. It need not be normalized.
Uses: RTAR.
Exit: The two-byte signed two's complement representation of the integer
portion is left in M1 (high-order byte) and M1+1 (low-order byte). The
floating point values +24.63 and -61.2 are converted to the integers +24
and -61 respectively. FP1 and E are altered but FP2, E, SIGN, and SCR are
not. The A- and X-REGs are altered but the Y-REG is not.
Example: The floating point value +274 is in FP1 prior to calling FIX.
_____ _____ _____ _____
| | | | | | | |
FP1: | $88 | | $44 | | $80 | | 0 | (+274)
|_____| |_____| |_____| |_____|
X1 M1
After calling FIX, M1 (high-order byte) and M1+1 (low-order byte) contain
the integer representation of +274 ($0112).
_____ _____ _____ _____
| | | | | | | |
FP1: | $8E | | $01 | | $12 | | 0 |
|_____| |_____| |_____| |_____|
X1 M1
Note: FP1 contains an unnormalized representation of +274 upon exit.
NORM Subroutine (address $F463)
Purpose: To normalize the value in FP1, thus insuring maximum precision.
Entry: A normalized or unnormalized value is in FP1.
Exit: The value in FP1 is normalized. A zero mantissa will exit with X1=0
(2 exponent). If the exponent on exit is -128 (X1=0) then the mantissa
(M1) is not necessarily normalized (with the two high-order mantissa bits
unequal). E, FP2, SIGN, AND SCR are not distubed. The A-REG is disturbed
but the X- and Y-REGs are not. The carry is set.
Example: FP1 contains +12 in unnormalized form (as .0011 x 2 ).
_____ _____ _____ _____
| | | | | | | |
FP1: | $86 | | $0C | | 0 | | 0 | (+12)
|_____| |_____| |_____| |_____|
x1 M1
Upon exit from NORM, FP1 contains +12 in normalized form (as 1.1 x 2 ).
_____ _____ _____ _____
| | | | | | | |
FP1: | $83 | | $60 | | 0 | | 0 | (+12)
|_____| |_____| |_____| |_____|
X1 M1
NORM1 subroutine (address $F455)
Purpose: To normalize a floating point value in FP1 when it is known the
exponent is not -128 (X1=0) upon entry.
Entry: An unnormalized number is in FP1. The exponent byte should not be 0
for normal use.
Exit: The normalized value is in FP1. E, FP2, SIGN, and SCR are not not
disturbed. The A-REG is altered but the X- and Y-REGs are not.
ADD Subroutine (address $F425)
Purpose: To add the two mantissas (M1 and M2) as 3-byte integers.
Entry: Two mantissas are in M1 (through M1+2) and M2 (through M2+2). They
should be aligned, that is with identical exponents, for use in the FADD
and FSUB subroutines.
Exit: the 24-bit integer sum is in M1 (high-order byte in M1, low-order
byte in M1+2). FP2, X1, E, SIGN and SCR are not disturbed. The A-REG
contains the high-order byte of the sum, the X-REG contains $FF and the
Y-REG is not altered. The carry is the '25th' sum bit.
Example: FP1 contains +5 and FP2 contains +7 prior to calling ADD.
_____ _____ _____ _____
| | | | | | | |
FP1: | $82 | | $50 | | 0 | | 0 | (+5)
|_____| |_____| |_____| |_____|
X1 M1
_____ _____ _____ _____
| | | | | | | |
FP2: | $82 | | $70 | | 0 | | 0 | (+7)
|_____| |_____| |_____| |_____|
Upon exit, M1 contains the overflow value for +12. Note that the sign bit
is incorrect. This is taken care of with a call to the right shift
routine.
_____ _____ _____ _____
| | | | | | | |
FP: | $82 | | $C0 | | 0 | | 0 | (+12)
|_____| |_____| |_____| |_____|
ABSWAP Subroutine (address $F437)
Purpose: To take the absolute value of FP1 and then swap FP1 with FP2.
Note that two sequential calls to ABSWAP will take the absolute values of
both FP1 and FP2 in preparation for a multiply or divide.
Entry: FP1 and FP2 contain floating point values.
Exit: The absolute value of the original FP1 contents are in FP2 and the
original FP2 contents are in FP1. The least significant bit of SIGN is
complemented if a negation takes place (if the original FP1 contents are
negative) by means of an increment. SCR and E are used. The A-REG
contains a copy of X2, the X-REG is cleared, and the Y-REG is not altered.
RTAR Subroutine (address $F47D)
Purpose: To shift M1 right one bit position while incrementing X1 to
compensate for scale. This is roughly the opposite of the NORM subroutine.
Entry: A normalized or unnormalized floating point value is in FP1.
Exit: The 6-byte field MANT1 and E is shifted right one bit arithmetically
and X1 is incremented by 1 to retain proper scale. The sign bit of MANT1
(MSB of M1) is unchanged. FP2, SIGN, and SCR are not disturbed. The A-REG
contains the least significant byte of E (E+2), the X-REG is cleared, and
the Y-REG is not disturbed.
Caution: If X1 increments of 0 (overflow) then an exit to location $3F5 is
taken, the A-REG contains the high-order MANT1 byte, M1 and X1 is cleared.
FP2, SIGN, SCR, and the X- and Y-REGs are not disturbed.
Uses: RTLOG
Example: Prior to calling RTAR, FP1 contains the normalized value -7.
_____ _____ _____ _____
| | | | | | | |
FP1 | $83 | | $A0 | | 0 | | 0 | (-7)
|_____| |_____| |_____| |_____|
X1 M1
After calling RTAR, FP1 contains the unnormalized value -7 (note that
precision is lost off the low-order end of M1).
_____ _____ _____ _____
| | | | | | | |
FP1 | $84 | | $D0 | | 0 | | 0 | (-7)
|_____| |_____| |_____| |_____|
X1 M1
Note: M1 sign bit is unchanged.
RTLOG subroutine (address $F480)
Purpose: To shift the 6-byte field MANT1 and E one bit to the right (toward
the least significant bit). The 6502 carry bit is shifted into the
high-order M1 bit. This is useful in correcting binary sum overflows.
Entry: A normalized or unnormalized floating point value is in FP1. The
carry must be cleared or set by the user since it is shifted Into the sign
bit of M1.
Exit: Same as RTAR except that the sign of M1 is not preserved (it is set
to the value of the carry bit on entry)
Caution: Same as RTAR.
Example: Prior to calling RTLOG, FP1 contains the normalized value -12 and
the carry is clear.
_____ _____ _____ _____
| | | | | | | |
FP1: | $83 | | $A0 | | 0 | | 0 | (-12)
|_____| |_____| |_____| |_____|
X1 M1
After calling RTLOG, M1 is shifted one bit to the right and the sign bit is
clear. X1 is incremented by 1.
_____ _____ _____ _____
| | | | | | | |
FP1: | $84 | | $50 | | 0 | | 0 | (+20)
|_____| |_____| |_____| |_____|
X1 M1
Note: The bit shifted off the end of MANT1 is rotated into the high-order
bit of the 3-byte extension E. The 3-byte E field is also shifted one bit
to the right.
RTLOG1 subroutine (address $F484)
Purpose: To shift MANT1 and E right one bit without adjusting X1. This is
used by the multiply loop. The carry is shifted into the sign bit of
MANT1.
Entry: M1 and E contain a 6-byte unsigned field. E is the 3-byte low-order
extension of MANT1.
Exit: Same as RTLOG except that X1 is not altered and an overflow exit
cannot occur.
MD2 subroutine (address $F4E2)
Purpose: To clear the 3-byte MANT1 field for FMUL and FDIV, check for
inital result exponent overflow (and underflow), and initialize the X-REG
to $17 for loop counting.
Entry: the X-REG is cleared by the user since it is placed in the 3 bytes
of MANT1. The A-REG contains the result of an exponent addition (FMUL) or
subtraction (FDIV). The carry and sign status bits should be set according
to this addition or subtraction for overflow and underflow determination.
Exit: The 3 bytes of M1 are cleared (or all set to the contents of the
X-REG on Entry) and the Y-REG is loaded with $17. The sign bit of the
A-REG is complemented and a copy of the A-REG is stored in X1. FP2, SIGN,
SCR, and the X-REG are not disturbed.
Uses: NORM.
Caution: Exponent overflow results in an exit to location $3F5. Exponent
underflow results in an early return from the calling subroutine (FDIV or
FMUL) with a floating point zero in FP1. Because MD2 pops a return address
off the stack, it may only be called by another subroutine.