WD1770 disk controller
WD1770/2/3 data (disk controller chip)
======================================
This file contains essential data on programming the floppy disk controller
chip used in BBC B+, Master, BBC B with Opus DDOS and some Archimedes
computers. Please note that a lot of the information in the relevent data
sheet has had to be cut out. You are advised to mail this file to yourself,
as it is rather long (about 10 pages).
Register summary
================
Address offset Contains on read on write
------------------------------------------------------
0 Status Command
1 ------- Track --------
2 ------- Sector -------
3 ------- Data ---------
Command summary
===============
Command register bits
Type Command 7 6 5 4 3 2 1 0
-------------------------------------------------------
I Restore 0 0 0 0 h v r1 r0
I Seek 0 0 0 1 h v r1 r0
I Step 0 0 1 u h v r1 r0
I Step in 0 1 0 u h v r1 r0
I Step out 0 1 1 u h v r1 r0
II Read sector 1 0 0 m h/s e 0/c 0
II Write sector 1 0 1 m h/s e p/c a
III Read address 1 1 0 0 h/0 e 0 0
III Read track 1 1 1 0 h/0 e 0 0
III Write track 1 1 1 1 h/0 e p/0 0
IV Force interrupt 1 1 0 1 i3 i2 i1 i0
Where :
h = motor spin-up sequence disable flag. (1770/2 only)
= 0 Enable spin-up sequence if motor is currently not running.
= 1 Disable spin-up sequence.
v = verify on destination flag. (all)
= 0 Do not verify
= 1 Verify (adds a 30 msec head settling time onto command execution)
r1,r0 = head track-to-track stepping rates. (all)
r1 r0 1770/3 1772
0 0 6 ms 6 ms
0 1 12 ms 12 ms
1 0 20 ms 2 ms
1 1 30 ms 3 ms
u = update track register. (all)
= 0 Do not update track register
= 1 Update track register.
m = multiple sector read/write flag. (all)
= 0 read/write 1 sector only.
= 1 read/write sectors on current track until command is interrupted
using the FORCE INTERRUPT command.
s = side compare flag (1773 only)
= 0 Compare for side 0.
= 1 Compare for side 1.
a0= data address mark type. (all)
= 0 Write normal data mark.
= 1 Write deleted data mark.
e = Head settling delay. (all)
= 0 No delay
= 1 Add 30 ms delay (15 ms on 1772)
c = Side compare flag. (1773 only)
= 0 Disable side compare.
= 1 Enable side compare.
For all type III commands bit 1 must be 0
p = Write precompensation flag. (all)
= 0 Enable write precompensation.
= 1 Disable write precompensation.
i3= 1, immediate interrupt. (all)
i2= 1, interrupt on every index pulse. (all)
i1= 1, Ready to not ready transition. (1773 only)
i0= 1, Not ready to ready transition. (1773 only)
Data formats:
=============
Read address.
Byte Contains
---------------------------
0 Track number
1 Side number
2 Sector number
3 Sector length
4 CRC check byte (1)
5 CRC check byte (2)
Write track (format a track)
Double density formats:
=======================
Recommended | Acorn ADFS |
format | (master 128) |
No. of Hex value | No. of Hex value |
bytes to write | bytes to write | Info
-----------------------+----------------------+-------------------------------
60 4E | 60 4E | Post-index Gap (Gaps 1+2)
/ 12 00 | / 12 00 | Pll lock-up time
| 3 F5 | | 3 F5 | 3 synchronisation bytes
| 1 FE | | 1 FE | ID address mark
| 1 | | 1 | Track number
| 1 | | 1 | Side number
| 1 | | 1 | Sector number
| 1 | | 1 01 | Sector length
| 1 F7 | | 1 F7 | Writes 2 CRC bytes
| 22 4E | | 22 4E | Sector ID / Data Gap (Gap 3a)
| 12 00 | | 12 00 | /Write splice time (Gap 3b)
| | | | \Pll lock-up time
| 3 F5 | | 3 F5 | 3 synchronisation bytes
| 1 FB | | 1 FB | Data address mark
| n | | 256 (5A on format)| Data (number of bytes depends
| | | | on the sector length)
| 1 F7 | | 1 F7 | Writes 2 CRC bytes
\ 24 4E | \ 43 4E | Post Data Gap (Gap 4)
668 approx 4E | 4E | Runout Gap. Write until
| | next index hole.
Single density formats:
=======================
Recommended | Acorn 1770 DFS 2.24 |
format | (master 128) |
No. of Hex value | No. of Hex value |
bytes to write | bytes to write | Info
----------------------+----------------------+--------------------------------
40 FF | 40 FF | Post index Gap (Gaps 1+2)
/ 6 00 | / 6 00 | Pll lock-up
| | | 3 F5 | 3 synchronisation bytes
| 1 FE | | 1 FE | ID address mark
| 1 | | 1 | Track number
| 1 | | 1 | Side number
| 1 | | 1 | Sector number
| 1 | | 1 01 | Sector length
| 1 F7 | | 1 F7 | Writes 2 CRC bytes
| 11 FF | | 10 4E | Sector ID / Data Gap (Gap 3a)
| 6 00 | | 4 00 | Pll lock-up (Gap 3b)
| | | 3 F5 | 3 synchronisation bytes
| 1 FB | | 1 FB/F8 | Data address mark
| n | | 256 (5A on format)| Data
| 1 F7 | | 1 F7 | Writes 2 CRC bytes
\ 10 FF | \ 10 FF | Post data Gap (Gap 4)
369 approx FF | FF | Runout Gap. Write until
| | next index hole.
Write the bracketed area the following times:
Sector length Sector size (n) Number of times to write
-------------------------------------------------------------
00 128 ?
01 256 16 (ADFS 16, DFS 10)
02 512 ?
03 1024 5
Notes
1) The gaps can be altered to a minimum of:
Single density Double density
Gap 1 16 32
Gap 2 11 22
Gap 3a 10 24
Gap 3b 4 8
Gap 4 10 16
2) The reliability depends on the gaps. For highest reliability,
use the recomended formats.
3) The 177X will not automatically detect which density it is use.
There is usually a separate register or a hard link to set up the
denstiy. This applies to all commands.
Status register.
================
The meaning of the bits in the status register depends on which type of
command is currently executing.
Bit | Type I | Type II | Type III | Comments
----+------------------+---------------+---------------+-------------------
7 | Motor on | ---------- Motor on --------- | / If bit 3 is
6 | Not used. | -- Disk is write protected. - | | set then:
5 | Motor spin-up | Data type : 0 = normal. | | If bit 4 is
| completed. | 1 = deleted. | | set, the error
4 | Record not found | ----- Record not found ------ | / is in the ID
3 | CRC error. | --------- CRC error --------- |< field. If bit 4
2 | Not track 0 | ------ Lost data / byte ----- | \ is clear, the
1 | Data Request | -------- Data request ------- | | error is in
0 | Busy | ------------ Busy ----------- | \ the data field.
Note that after a reset, some 177X's say that they are busy, when they are
idle. This happens when you reset the chip while a command is in progress.
Read/Write delay times
======================
There are certain delay times that must be taken into account:
Operation Next operation Delay required
Single Double density
----------------------------------------------------------------
Write command / Read busy bit 48 usec 24 usec
register \ Read status bits 1-7 64 usec 32 usec
Write any reg Read same register 32 usec 16 usec
Drive control register
======================
This controls various functions that the 177X is unable to:
Master drive control:
Bit Meaning
-----------------
7,6 Not used.
5 Double density select (0 = double, 1 = single).
4 Side select (0 = side 0, 1 = side 1).
3 Drive select 2.
2 Reset drive controller chip.
1 Drive select 1.
0 Drive select 0.
B+ drive control:
Bit Meaning
-----------------
7,6 Not used.
5 Reset drive controller chip.
4 Interrupt ?
3 Double density select (0 = double, 1 = single).
2 Side select (0 = side 0, 1 = side 1).
1 Drive select 1.
0 Drive select 0.
Opus double density board on BBC:
Bit Meaning
-----------------
7 Not used.
6 Density select (0 = single, 1 = double).
5-2 Not used.
1 Side select (0 = side 0, 1 = side 1).
0 Drive select (0 = drive 0, 1 = drive 1).
Note that only 1 drive select bit line should be set at a time.
Addresses of registers:
=======================
Computer Location of disk chip & chip Location of drive control
---------------------------------------------------------------------
BBC B with Opus &FE80 - &FE83 WD1770 &FE84
BBC B+ &FE84 - &FE87 WD1770 &FE80
BBC Master &FE28 - &FE2B WD1770 &FE24
Archimedes ? WD1772 ?
I am aware that some archimedes used the WD1772 is used, but if anyone
knows the addresses, I will be happy to put them in.