IMD 1.18: 1/10/2013 7:38:07 Fortune Diagnostics Bootable Vol 1 of 1 FCS Boot Format Floppy #1 NuNV f"-n N^NuNV f(R N^NuNV N^NuNV N^NuNV N^NuNV NuNV N^NuNV N^Nu N^NuNV N^NuNV N^NuNV H`2# N^NuNV g2 - Hh*| *L(U N^NuNV `>/< N^NuNV N^NuNV N^NuNV ,NuNV a\&| a`(< H`Hn BG`$0 BG`f0 @ PN @/( A!@ HP/< HP/< H`/< @ PN @ ( J. $@BF` N^NuNV N^NuNV g"(M*U N^NuNV N^NuNV #D @ #D @ N^NuNV N^NuNV N^NuNV @/( U h N^NuNV g, UJ a` @/( U h g0 UJ @/( U h N^NuNV g< UJ g4/. a` @/( U h g@ UJ g8/. @/( U h N^NuNV @/( U h N^NuNV @/( U h N^NuNV a` @/( P h N^NuNV a` @/( P h N^NuNV N^NuNV @-P N^NuNV ah*@J N^NuNV ah*@J N^NuNV N^NuNV ah(@J DgB l HU/, N^NuNV N^NuNV HTHn N^NuNV g. n `|/< eB/< @`$&JJSg N^NuNV N^NuNV nNHn N^NuNV N^NuNV ah*@J `J - N^NuNV `h m Dg,`./< m"Hm N^NuNV N^NuNV Dg6 m DgJ~ N^NuNV ah(@J 6HUN `&/. N^NuNV o` . mFHn ` /. N^NuNV N^NuNV `v n JPfHSl N^NuNV HT/. N^NuNV N^NuNV (A . g"HT/. N^NuNV a`$| @/( @ h HUHn BE` 7n 0 rRF0 @/( @ h HUHn BE` 7n 0 HU/< N^NuNV ah*@ @J( ah`$ m: . N^NuH Ns/< Nu / Nu"< NuNsH / /< Nua1 %X a0 %X d1 %X d0 %X a2 %X a3 %X a4 %X a5 %X a6 %X a7 %X d2 %X d3 %X d4 %X d5 %X d6 %X d7 %X TException %D bus error SP %X addr error SP %X SSW %x addr %X IR %x SR %x PC %X Halted gNJ9 f,/9 `./< N^NuNV ah*@ gzHU/. g* m N^NuNV ah*@J N^NuNV a`&| @/( @ h `r . @/( @ h N^NuNV ah*@ DHU/. `JHU0 Hp/< 8N^NuNV N^NuNV N^NuNV N^NuNV "HU0. a` @/( VHUN N^NuNV N^NuNV N^NuNV N^NuNV N^NuNV N^NuNV N^NuNV N^NuNV N^NuNV N^NuNV N^NuNV N^NuNV N^NuNV N^NuNV N^NuNV 9N^NuNV N^NuNV N^NuNV N^NuNV N^Nu N^NuNV ` '| Hx'@ ` '| N^NuNV ah*@J `0J- N^NuNV N^NuNV nnBl g*&| N^NuNV $H&n ah*@HUHTN f6/< xN^NuNV ah&@B >R, HT m gL 9 9`0& (h @0 &HUN N^NuNV &P<, g /< HU/< `>9k N^NuNV (P&m OHUN N^NuNV &P$k g4>, HSHUN (X @0 PHR m lHSN HS m "HR m PHR m N^NuNV N^NuNV N^NuNV l$ . @*P (h @0 N^NuNV N^NuNV N^NuNV &P/< $H , HTHSHUN HT m N^NuNV g00+ (h A2 HTHUN HT m N^NuNV lh . @*P gL0- (h A2 g*/< N^NuNV ld . @*P gH0- (h A2 (X @0 HSHUN HR m HUN HS m "HR m @f HSHUN N^NuNV P`4$K HR m N^NuNV f:/< f20. f 0. N^NuNV N^NuNV (@g0J HU/< HTHUN N^NuNV .HUN l$H%y "`,/ PHUN N^NuNV N^NuNV f8/< `"/. N^NuNV HT m N^NuNV 1AYf2 - f$ - N^NuNV N^NuNV 9`t0 HTHSHUN 9HTN N^NuNV &PJk N^NuNV P$HA fZ n (X @0 Nf p N^NuNV N^NuNV 'HTHUN N^NuNV y A$| )X(AJ )X(A (@/< HRHSN HTHSHUN N^NuNV @JPm N^NuNV $PJj (@/< 9HT` "`4/< HSHRHUN HTHRHUN N^NuNV 9`t/, HSHTHUN 9HSN N^NuNV +| N^NuNV N^NuNV 0d$< 9`fJ N^NuNV &@ @ P0( "HTN "HTA N^NuNV g*/, g*HUN HTHUN N^NuNV (P n N^NuNV N^NuNV HU/< N^NuNV @HUN &HUN (P - HTHUN HTHUN (PHTHUN N^NuNV "f$+| HTHUN HTHUN jHTN N^NuNV HTHUN N^NuNV y A+| N^NuNV y A+| N^NuNV N^NuNV HT/< S0( N^NuNV N^NuNV N^NuNV "f<9m N^NuNV N^NuNV tHTN tHTN y A` y A+F HTHUN tHTN HTHUN &fPJ HTHUN HTHUN HTHUN HTHUN m\0+ "HSN HTN tf& "HSN N^NuNV HTHUN N^NuNV &HHSHUN N^NuNV &HHSHUN HTHUN N^NuNV N^NuNV N^NuNV N^NuNV y A/< fF/< N^NuNV N^NuNV gt0. &P . f:/< 1$/< (@HTHSHUN HTHSHUN HSHUN HTHSHUN HTHSHUN HTHSN y A09 fR/< f$/< N^NuNV y A09 fD/< f$/< N^NuNV y A/< N^NuNV f$/< N^NuNV `@,< N^NuNV N^NuNV N^NuNV HTHSN HTHSN |HSHUN N^NuNV &HHSHUN N^NuNV tHUN N^NuNV &@HSHTHUN HTHUN HSHTHUN N^NuNV HSHUN "HSHTN N^NuNV HSHUN "HSHTN N^NuNV N^NuNV 1AYfH - f: - (@-l HT/< N^NuNV (@-l HT/< N^NuNV N^NuNV f +m HU/< N^NuNV N^NuNV HTHUN HTHUN tHUN g"+m HU/< N^NuNV N^NuNV N^NuNV y Qf N^NuNV N^NuNV bHUN N^NuNV cHUN N^NuNV N^NuNV HTHUN N^NuNV gP| `. "@#h @!n N^NuNV N^NuNV N^Nu rigid rigid no more spares Drive %d has gone bad, will not accept any more requests floppy 2rfd floppy Drive %d type is invalid: %d FDINIT: recalibrating drives FDINIT: past first wait FDINIT: timeout on recalibrate FDINIT: unit %d failed FDINIT: ready change on unit %d FDINIT: invalid ST0 = 0x%x FDINIT: last unit = %d (exist = 0x%x) FDINIT: done, infop = 0x%X FDCINIT: infop = 0x%X FDOPEN: no such unit/parition (dev = 0x%x) FDOPEN: cannot open since it's hung FDOPEN: open for wrong type FDOPEN: before rdconf for %d/%d FDOPEN: NODIS N^NuNV N^NuNV B@H@ H@`6 " is displayd on the CRT. 6) Type h ( for help ). A set of commands are displayed on the CRT. The display explains what FORTUNE OPERATING SYSTEM features are available. 7) Type I ( I for initialization ) to initialize the hard disc. 8) Type T ( T for trap vertor ) to initialize the trap vectors. 9) Type 1000: . 10) Type 0,40000F. This clears memory locations 0x1000 thru 0x40000. 11) Now we are ready to down load the diagnostic program from the host computer to the FORTUNE system. 12) Type H ( H for host computer ). This puts the FORTUNE SYSTEM under the control of the host computer, namely VAX. 13) Type dld coma. This down loads the diagnostic program from VAX on to the FORTUNE SYSTE 1 4 1 8 19200 odd ----------------------------------------------------------------------------- 5.2 Stop Bits Tests TABLE 2 ********************** Group Test Number Stop Bits Character Size Baud Rate Parity 2 1 1 8 19200 odd 2 2 1.5 8 19200 odd 2 3 2 8 19200 odd ---------------------------------------------------------------------------- 5.3 Parity Tests TABLE 3 ********************** Group Test Number Stop Bits Character Size Baud Rate Parity 3 1 1 5 19200 odd 3 2 1 5 19200 even 3 3 1 5 19200 none 3 4 1 6 19200 odd 3 5 1 6 19200 even 3 6 1 6 19200 none 3 7 1 7 19200 odd 3 8 1 7 19200 even 3 9 1 7 19200 none 3 10 1 8 19 M's memory. 14) The message " completed " is displayed on the CRT, when down loading has completed. 15) Now we are ready to save the diagnostic program on to the 5 mega/byte hard disk. 16) Type 1000 900 80S. This saves the diagnostic program on to the hard disk. The operator is prompted with "done", when saved. Once a copy of the diagnostic program is on disc, a fresh copy of the program can be quickly read back into memory. This is useful when the FORTUNE system is powered down to switch boards. 17) Type 1000G. The operator is prompted with " COMM-A: ". 18) Enter a Carriage Return (CR). This causes all COMM-A diagnostic tests to be executed automatically. Currently, channels 0 & 1 of DART chip 0 and channels 2 & 3 of DART chip 1 of the COMM-A board in slot C are tested. If more than one board is being tested, refer to the section 1.1, Hardware Environment Command to set the corresponding parameters. 19) A PASSED/FAILED message is displayed after each t 200 odd 3 11 1 8 19200 even 3 12 1 8 19200 none ---------------------------------------------------------------------------- 5.4 Baud Rate Tests TABLE 4 ********************** Group Test Number Stop Bits Character Size Baud Rate Parity 4 1 1 8 50 odd 4 2 1 8 75 odd 4 3 1 8 110.2 odd 4 4 1 8 134.5 odd 4 5 1 8 150 odd 4 6 1 8 300 odd 4 7 1 8 600 odd 4 8 1 8 1200 odd 4 9 1 8 1800 odd 4 10 1 8 2400 odd 4 11 1 8 4800 odd 4 12 1 8 9600 odd 4 13 1 8 19200 odd --------------------------------------------------------------------------- TEST OPERATION PROCEDURE ************************** est completes. A brief description of the test is also included in the message. Refer to the the PASSED/FAILED message, secetion 2 for more information. 20) In order to test the next board(s), power down the FORTUNE SYSTEM and replace the tested board(s) with the new board. 21) Power up the FORTUNE SYSTEM. 22) Press the reset key. 23) Type I to initialize the hard disc. 24) Type 1000 900 80R. This reloads the diagnostic program from the hard disc into FORTUNE SYSTEM memory. 25) The operator is prompted with ' done '. 26) Now repeat the steps 17 and after. N^NuN ~(BG Y @B Y @J ~( y N^NuN ~( y N^NuN ~( y N^NuN ~( y ~COPYRIGHT 1982 FORTUNE SYSTEMS CORPORATION. DISCLOSURE TO OTHERS PROHIBITED. FOR TERMS OF USE REFER TO LICENSE AGREEMENT. N^NuN N^NuN ~,By N^NuN N^NuN ~( y N^NuN N^NuN N^NuN ~(Bn Y @J Z @# ~(-| ~(-| N^Nu N^NuN ~(/< Y @J N^NuN ~( y N^NuN ~(BG BFBG ~( y N^NuN vv0< vv0< vvB@` N^Nu vv n N^NuN ~( y BEBG ~( y N^NuN ~( y N^NuN ~( y N^NuN BG n BPB@` N^NuN *@ n N^NuN (@>. *@ n N^NuN N^NuN N^Nu *@ . *@ . N^Nu vv n @"n @"n @"n @"n @"n , @"n @"n > @"n @"n @"n @"n vv . N^NuN @"n ,SG` @"n @"n @"n ~=|> @"n @"n @"n @"n @"n @"n @"n @"n P @"n @"n @"n @"n N^Nu @"n b @"n h n :Rn @"n t @"n @"n @"n N^Nu | @ . N^NuN @d/< N^NuN x*@ . N^NuN x*@ . N^NuN *@ . N^Nu @ . @< n ?t . |H @"n =F . |R @"n @ . @ . @ @ . |\ @"n :R . :& . |f @"n 9X n 8d . -^J9 |p @"n 6* . |z @"n 4h . +:J9 @"n 36 . p ` @"n 2< n 1t . 1H . @"n '^ . %: . $h n "D n n @"n @"n @"n @"n @"n L/< $ n N^NuN (@Bn *HRC0 N^NuN HSHm HTHm N^NuN N^NuN P(@N ^gT`X 2~{` N^NuN N^Nu NuNuNu N^Nu _ `H o R@NuB R@NuB R@Nu N^NuN (HUN N^NuN N^NuN N^NuH @"@$@&@(@*@,@B "L0< @"@$@&@(@*@,@ < HABA N^Nu H@`6 N^Nu HABA N^NuNV B@H@ B@H@` N^Nu@(#)diag_copyrt.s 1.4 @(#)diag_srt.s 1.3 @(#)comb.c 3.6 Standalone Comm-B Test & Verification package, ver 3.3 8-8-83 General command format is: [arg1] [arg2]; ... Use 'HELP'...to reprint this summary Use 'DEL'....to terminate testing after the current test a(ddr).......arg1-arg5 are the option slots to test: abcde if no arg1, option slot 'C' is selected c(ount)......arg1 is the number of times to repeat each test d(isplay)....prints all curren A J"J:< J"J` "J < x(HB. n&HJ x&H x(H` DN^NuN tly selected options e(xternal)...loopback testing selected for test 'd' -e(xternal)..test 'd' reverts to internal loopback SIO testing g(o).........executes selected tests l(oop).......if arg1 is 'e', sets test to loop on first error 'a' sets selected test(s) to loop till killed 'f' arg sets selected test(s) to loop till first error -l(oop)......turns off loop mode p(ause)......on any error untill the space bar is pressed -p(ause).....turns off pause on error mode q(uit).......exits to boot prompt ':' r(ange)......arg1,arg2 are starting, ending word address' for test 6 missing arg(s) default to top and/or bottom of memory acceptable values are 00-077777,0-32767,0x0-0x7fff t(est).......arg(s) or arg-arg select test(s) or range of tests to be run, if no arg prints description of all tests and selects to run all tests. Enter test #'s '1-d'(hex) unrecognized command Unrecognized command 012345678 ure (Loop-back Connector) must be installed on each RS232 connector for correct test operation. 123456789abcd invalid test number: %c Try 1-%x 123456789abcd invalid test number: %c Try 1-%x out-of-order arguments: %x %x Try again a '-' command requires an 'e' or 'l' argument invalid argument: -%c no pause argument expected: %c @(#)comb_t11.c 3.2 @(#)comb_t12.c 3.1 @(#)comb_t13.c 3.2 @(#)comb_t14.c 3.1 @(#)comb_t15.c 3.1 @(#)comb_t16.c 3.2 @(#)comb_t17.c 3.1 @(#)comb_t18.c 3.2 @(#)comb_t21.c 3.1 @(#)comb_t22.c 3.1 :200000000006140E0016001E55213F000C737EBB20260C23733A0000BA201D0CCB25CB1423 :1D0020002B723A3F00BB201078FE0B20077B2F5F213F007310DC0E00793200007623 :00000001FF @(#)comb_t23.c 3.1 :0400000031FEFF0 9abcdef invalid numeric argument: %s @(#)comb_cmd.c 3.3 1 - Test 1.1 - Self-Test Execution 2 - Test 1.2 - Interface Registers 3 - Test 1.3 - Dual-Port Ram Test w/o Refresh 4 - Test 1.4 - Dual-Port Ram Parity Logic 5 - Test 1.5 - Z-80 Instruction Execution 6 - Test 1.6 - Dual-Port Ram Test with Refresh 7 - Test 1.7 - Z-80 NMI Logic 8 - Test 1.8 - Dual-Port Ram Memory Fading 9 - Test 2.1 - Z-80 I/O Address Bus a - Test 2.2 - Z-80 Memory Address Bus b - Test 2.3 - Dual-Port Ram Test with CLB Accesses c - Test 2.4 - Interrupt Handshake Logic d - Test 2.5 - CTC and SIO Logic CommB's under test= Tests to be run= Repeat count= %d Looping on error Looping on selected test(s) and slot(s) until the first error occurrs Looping on selected test(s) and slot(s) regardless of error occurrences Loop mode disabled Total errors= %d Starting addres :20000400CDB001F5F5218402227402973270023EF8327102973272023273023A7202D610A7 :200024003A7302DE00F257000150022A7202097EDD77F72172027E23B6C273002A7002E581 :200044002A7402E5DD7EF74F879F476960CD2201C38F00DD36F800DD36F900210000E521C0 :200064000000E5DD6EF8DD66F9CD6201C3C7012A7002E52A7402E5DD7EF64F879F47C5DDA8 :200084007EF74F879F476960CDA4000150022A7202097EDD77F62A720223227202C31F00F6 :2000A400CDDD01F5F5DD6E08DD6609227402DD6E0ADD660B227002DD7E06327202879F32DA :2000C4007302DD7E04DD77F92174023A7002963A7102239EDA0F012A74027E5F879F5721AF :2000E40072027BBE20037A23BE2823DD36F602DD36F7002A7202E52A74027E4F879F47C54F :20010400DD6EF6DD66F7CD62011803C335022A7402E523227402E1DD7EF977C3CC00CDDDF6 :2001240001DD7E04327402879F327502DD6E06DD6607227002DD6E08DD66092272022170EF :20014400023A7202963A7302239E380F2A7002E523227002E13A74027718E3C31B02CD05B1 :200164000221F4FF39F9DD36F800DD36F900DD36F602DD36F700DD36F403DD36F500DD6EAA :20018400F8DD66F9DD7E0477DD6EF6DD66F7DD7E0677DD6EF4DD66F5DD7E0877CDA601C376 :2001A4001202CDF601F5F5F5F57618F s= %x Ending address= %x Window= High Window= Low Test Window= All of Memory Test Window= Low Window to High Window Test Window= High Window Only Test Window= Low Window Only External Loopback Testing is Selected. The Special Test Fixture (Loop-back Connector) must be installed on each channel. Internal Loopback SIO Testing is Selected Pause on Error Selected Pause on Error Not Selected Slot %c will be tested abcde ABCDE invalid slot letter: %c error: address range is WIND_HI to WIND_LO invalid loop argument: %c Testing has been terminated. Slot number: %c Test number: %x Pass number: %d Errors: %d Passed Slot number: %c Test number: %x Pass number: %d Failed stat= %d adr= %x exp= %x act= %x win= %d errs= %d stat= %d adr= %x exp= %x act= %x win= %d pass= %d errs= %d Slot number: %c Test number: %x Pass number: %d Failed stat= %d adr= %x exp= %x act= %x win= %d errs= %d no argument expected External loopback testing is selected. The Special Test Fixt DD1DDE5DD210000DD392A7402E52A7202E52A7002B9 :2001C400E5EBE911FAFFDD19DDF9E1227002E1227202E1227402DDE1C9D1E3E5DDE5DD2147 :2001E4000000DD392A7402E52A7202E52A7002E5EBE9E1DDE5DD210000DD39E9DDF9DDE154 :20020400C9D1E3E5DDE5DD210000DD39EBE9DDF9DDE1E1F1F1F1E911FAFFDD19DDF9E122C4 :200224007002E1227202E1227402DDE1E1F1F1F1E911FAFFDD19DDF9E1227002E12272023B :0C024400E1227402DDE1E1F1F1F1F1E9E9 :200250000102040810204080FEFDFBF7EFDFBF7F0000000000000000000000000000000096 :0602700000000000000088 :00000401FB @(#)comb_t24.c 3.1 @(#)comb_t25.c 3.4 :0400000031FEFF00CE :20000400CD720421F2FF39F9DD36F601DD36F727DD7EF6B7CA8000DD36F4F8DD36F500DDE4 :200024004EF79747C5DD6EF4DD66F5CD6C04DD4EF69747C5DD6EF4DD66F5CD6C043E02D395 :20004400F8DD7EF6DD77F9DD6EF4DD66F5CD6604DD71F8DD36F220DD36F300DD7EF8DDBEF9 :2000640 003C40021F700CD6C04DD4EF99747C521F700CD6C04210200E521F700CD6C0421F700CD66 :2003E4006604DD71F8DD34F22003DD34F3DD7EF8DDBEF92815DD4EF99747C5DD4EF8974733 :20040400C5DD6EF2DD66F3CD1804DD7EF687DD77F6C31400CD810421F4FF39F9DD36F8001B :20042400DD36F900DD36F602DD36F700DD36F403DD36F500DD6EF8DD66F9DD7E0477DD6EE5 :20044400F6DD66F7DD7E0677DD6EF4DD66F5DD7E0877CD5C04C38E04CD7204F5F5F5F57630 :2004640018FD4DED480600C94DE1D1ED59E9E1DDE5DD210000DD39E9DDF9DDE1C9D1E3E54E :13048400DDE5DD210000DD39EBE9DDF9DDE1E1F1F1F1E98A :00000401FB :0400000031FEFF00CE :20000400CD720421F2FF39F9DD36F601DD36F727DD7EF6B7CA8000DD36F4ECDD36F500DDF0 :200024004EF79747C5DD6EF4DD66F5CD6C04DD4EF69747C5DD6EF4DD66F5CD6C043E02D395 :20004400ECDD7EF6DD77F9DD6EF4DD66F5CD6604DD71F8DD36F22ADD36F300DD7EF8DDBEFB :20006400F9CAA800DD4EF99747C5DD4EF89747C5DD6EF2DD66F3CD1804C3A800DD36F200B8 :20008400DD36F300DD36F800DD36F900DD4EF99747C5DD4EF89747C5DD6EF2DD66F3CD185A :2000A40004C37C04DD6EF97D2F6FDD75F9DD4EF79747C5DD6EF4DD66F5CD6C04DD4EF99717 :2000C40047C5DD6EF4DD66F5CD6C0 0F9CAA800DD4EF99747C5DD4EF89747C5DD6EF2DD66F3CD1804C3A800DD36F200B8 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:1E0401004028232973696F6D332E6309312E3100464F5254554E452033323A313600CB :00000801F7 :0800000031FEFF003E07D3BCF6 :20000800CD8C0321E4FF39F9DD36E6BE21DF00CD8003DD71F9DD6EF97DE6202820DD36F7DF :2000280000DD7EF9DD77F8DD4EF79747C5DD4EF89747C5DD4EE697476960CD3203DD36E6DA :20004800BFDD6EF97 9DDE1E1F1F1F1E91B :1E03B1004028232973696F64312E6309322E3100464F5254554E452033323A31360026 :00000801F7 NOTE: DART channels 'C' and 'D' are not tested with internal loopback selected External loopback must be selected via the (e)xternal command @(#)load.c 3.1 @(#)printf.c 1.1 (null) @(#)diag_gets.c 2.3 DEL @(#)diag_csavret.s 1.3 @(#)diag_initcrt.c 1.2 DE6082820DD36F700DD7EF9DD77F8DD4EF79747C5DD4EF89747C5DDD0 :200068004EE697476960CD3203DD36E6C0DD6EF97DE6102820DD36F700DD7EF9DD77F8DD5C :200088004EF79747C5DD4EF89747C5DD4EE697476960CD3203DD36F907DD4EF99747C521F5 :2000A800ED00CD8603DD36F912DD4EF99747C521ED00CD8603DD36F918DD4EF99747C521A0 :2000C800DF00CD8603DD4EF99747C521DF00CD8603DD36F910DD4EF99747C521DF00CD8690 :2000E80003DD36F902DD4EF99747C521DF00CD8603DD36F910DD4EF99747C521DF00CD8694 :2001080003DD36F904DD4EF99747C521DF00CD8603DD36F987DD4EF99747C521DF00CD86FA :2001280003DD36F903DD4EF99747C521DF00CD8603DD36F9E1DD4EF99747C521DF00CD8681 :2001480003DD36F905DD4EF99747C521DF00CD8603DD36F9EADD4EF99747C521DF00CD8656 :2001680003DD36F905DD4EF99747C521DF00CD8603DD36F9EADD4EF99747C521DF00CD8636 :2001880003DD36F910DD4EF99747C521DF00CD8603DD36F901DD4EF99747C521DF00CD86F4 :2001A80003DD36F914DD4EF99747C521DF00CD86033E05ED47ED5EFBDD36E6C121DF00CDB3 :2001C8008003DD71F9DD6EF97DE6206FFE202820DD36F720DD7EF9DD77F8DD4EF79747C522 :2001E800DD4EF89747C5DD4EE697476960CD3203DD36E6C2DD6EF N^NuN N^NuN '`/< N^NuN '`/< N^NuN N^NuN @m"B N^NuN 97DE6086FFE082820DD73 :2002080036F708DD7EF9DD77F8DD4EF79747C5DD4EF89747C5DD4EE697476960CD3203DDDF :2002280036E6C3DD6EF97DE6106FFE102820DD36F710DD7EF9DD77F8DD4EF79747C5DD4EB1 :20024800F89747C5DD4EE697476960CD3203DD36E6C4DD36E800DD36E920DD36E701DD7E17 :20026800E7FE0ED2A60221C103DD5EE79757197E4F879F47C521DE00CD8603DD36E4FFDDD4 :2002880036E50FDD7EE4DDB6E5CAD102DD7EE4D601DD77E4DD7EE5DE00DD77E518E5DD3623 :2002A800E600DD36F800DD36F700DD4EF79747C5DD4EF89747C5DD4EE697476960CD3203F6 :2002C800C39603DD34E7C36602DDE5C121EAFF09DD5EE7975719DD4EE8DD46E90A77DDE576 :2002E800C121EAFF09DD5EE7975719E521C103DD5EE7975719C10ABECACB0221C103DD5EC6 :20030800E79757197E4F879F47C5DDE5C121EAFF09DD5EE79757197E4F879F47C5DD4EE619 :2003280097476960CD3203C3CB02CD9B0321F4FF39F9DD36F800DD36F900DD36F602DD3696 :20034800F700DD36F403DD36F500DD6EF8DD66F9DD7E0477DD6EF6DD66F7DD7E0677DD6E99 :20036800F4DD66F5DD7E0877CD7603C3A803CD8C03F5F5F5F57618FD4DED480600C94DE181 :20038800D1ED59E9E1DDE5DD210000DD39E9DDF9DDE1C9D1E3E5DDE5DD210000DD39EBE915 :0903A800DDF N^NuN N^NuN 04$< `l2 04/< N^NuN N^NuN N^NuN N^NuN 'dJn `Z . # f [arg1] [arg2];.. Use 'HELP'.....to reprint this summary Use 'DEL'......to terminate testing after the current test a(ddress)......arg1-arg5 are the o information will be displayed by typing 'd'. These default values can be changed using the various commands described below. The test command 't' allows the selection of a particular test or tests. A range of tests can be selected by separating the starting and ending test values with a dash (-). If the following command line is entered; "t " FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 3 with no arguments, all tests will be selected to be run and the following information displayed: 1 - Test 1.1 - Self-Test Execution 2 - Test 1.2 - Interface Registers 3 - Test 1.3 - Dual-Port Ram Test w/o Refresh 4 - Test 1.4 - Dual-Port Ram Parity Logic 5 - Test 1.5 - Z-80 Instruction Execution 6 - Test 1.6 - Dual-Port Ram Test with Refresh ption slots to test: abcde if no arg1, option slot 'C' is selected c(ount)........arg1 is the number of times to repeat each test d(isplay)......prints all currently selected options e(xternal).....loopback testing selected for test 'd' -e(xternal)....test 'd' reverts to internal loopback SIO testing g(o)...........executes selected tests l(oop).........if arg1 is 'e', sets test to loop on first error 'a' sets selected test(s) to loop till killed 'f' arg sets selected test(s) to loop till first error -l(oop)........turns off loop mode p(ause)........on any error untill the space bar is pressed -p(ause).......turns off pause on error mode q(uit).........exits to boot prompt ':' r(ange)........arg1,arg2 are starting, ending word addr 7 - Test 1.7 - Z-80 NMI Logic 8 - Test 1.8 - Dual-Port Ram Memory Fading 9 - Test 2.1 - Z-80 I/O Address Bus a - Test 2.2 - Z-80 Memory Address Bus b - Test 2.3 - Dual-Port Ram Test with CLB Accesses c - Test 2.4 - Interrupt Handshake Logic d - Test 2.5 - CTC and SIO Logic Examples of test command usage are; "t 2a 3-5 d" which would select tests 2 through 5, a and d to be run on every selected card and; "t b;g " which would select only test b and then execute the test. The range command 'r' is provided for selective memory testing. An example of its usage would be in the isolation of a suspected intermittent memory failure. The loop always command would be used in conjunction with the range command in this instance. The range arguments can be specified in octal, hexadecimal, or ided; loop until an error occurs, loop always, and loop on the first error that occurs. Entering the command line; "l e;g " provides the loop on error mode to be used on the first selected test that produces an error. Its effect on test execution is such that if an error occurs on a particular test that test will be repeated as long as the error persists. Note that an intermittent failure would eventually cause termination if only one test was selected otherwise the next selected test would be run. To break from the error looping condition the CANCEL/DEL key is pressed. If the command; "la;g " was entered the loop always mode would be initiated. This provides a means to continuously execute the selected test(s) on the selected slot(s) forever regardless of errors until the CANCEL/DEL key is pressed. If the command; "lf;g " was entered the loop decimal and address word (16-bit) locations in the shared memory, although the actual tests utilize both byte and word accesses. This command is used only with test 6. An example of its usage would be; "ac;t6; l;r 0x2000 0x2010;g " which in turn sets only the Comm 'B' card in slot C to be tested with test 6 over the 20 (hex) byte memory range 4000 (hex) to 4020 (hex). Note the necessary translation from bytes to words for correct command usage. This in turn limits the starting and ending byte address' to even values. Using the display command at this point would yield the test window information "Test Window= Low Window Only" which indicates that the memory test will be active only on the lower 32K bytes of shared memory. Other possible window information messages are "Test Window= All of Memory" which is the default memory test value, "Test Window= Low Window to High Window" which indicates that t he memory test will span both the upper and lower 32K byte windows, and "Test Window= High Window Only". FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 4 The address command 'a' allows the user to select a particular slot to be tested. If no arguments are used the default condition is performed with option slot 'C' selected for testing. An example of address command usage is; "a b D " which enables COMM 'B'cards in slots 'B' and 'D' to be tested. The quit command 'q' being executed results in an exit to the boot prompt ':' which then provides a means to boot another test, the standard operating system, etc. Additionally a system reset could be used at this time to allow normal system start-up. The loop command 'l' provides a means for COMM 'B' burn-in or system debug. Three loop modes are prov till first error mode would be initiated. This provides a means to loop forever until either an error occurrs or the CANCEL/DEL key is pressed to terminate testing. The negate loop command '-l' provides a means to terminate the selected loop mode. The pause on error command 'p' allows the user to examine the error information before continuing. Hitting the space bar resumes testing. The negate pause command '-p' provides a means to terminate the pause on error mode. The count command 'c' provides the means to repeat a FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 5 particular test or group of tests a selected number of times. The command will accept arguments in octal, hexadecimal, or decimal format. If no argument is used the default value of 1 is set. The count value is common to all t= 2 adr= ? exp= 0 act= ? page= 0 errs= 1 The error address is a long word pointer to one of five pre- specified locations (one location each for slots a-e). Status information is written to one of these locations depending on the FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 6 slot occupied. Upon successful completion of the self-test a '0' is written the the appropriate location. These address' are as follows: Slot 'a' -> address 'a44' Slot 'b' -> address 'a86' Slot 'c' -> address 'ac8' Slot 'd' -> address 'b0a' Slot 'e' -> address 'b4c' An error condition will return one of the following hex error values: 1 <>Indicates a checksum error. 2 <>Indicates a memory error. 3 <>Indicates an instruction execution error. Note that the special case selected COMM 'B's. The external loopback command 'e' provides a means for extended SIO and four-port communications adapter DART testing. The TTL to (+-)12V level translators are tested along with the RS-232 transmit, receive, sync/async, and modem control circuitry. The negate external loopback command '-e' reverts test 'd' back to internal loopback (main board SIO only) testing. _ 3. _ _ 1. _ 1: _ This test verifies the basic integrity of both the CLB and Z- 80 address, data, and control lines. The test consists of two parts: o The Prom is first checksummed using CLB accesses via 'C' code. o The driving program then vectors to, and executes, the Prom-based selftest code. This code consists of th in which no proms are installed will not produce a checksum error in either part 1 or part 2. _ 2. _ 2: _ This test verifies the integrity of the CLB command/status register and the 68000 interrupt vector register. The 12-bit command/status register provides a means for the 68000 to set some of the ComB board variables and to monitor the status of the ComB. This register is organized as follows: CLB Command/Status Register: D0 Software Latched Reset (0 = reset) D1 RAM Window (0 = lower 32k bytes) D2 Z80 Ack Mask (0 = interrupts enabled) D3 CLB Attn Mask (0 = interrupts enabled) D4 Forced Bad Parity (1 = bad parity being forced) D5 Undefined D6 Ack. Int.(to CLB) (0 = acknowledge interrupt pending) D7 Attn. Int.(to CLB) following sections: o The Prom is checksummed. o A shared memory confidence test is run. o The Z-80 is tested for basic instruction execution capability. The first part of Test 1.1 checksums the on-board EPROM using CLB accesses using 'C' code. This allows a controlled means of determining whether the Driver/Self-test code has degraded. The following error message is returned in case of failure: stat= 1 adr= ? exp= 0 act= ? page= 0 errs= 1 The address given will be the address of the last prom location summed. The actual value returned will reflect the erroneous summation value. The expected summation value is 0. The second part of this test has the driving program vector directly to the prom-based selftest code which it then executes. The following error message is returned in case of a failure: sta (0 = attention interrupt pending) D8 Expansion ID 1 D9 Expansion ID 2 D10 Latched NMI (1 = parity error since last cleared) D11 Z80 Halt Status (0 = Z80 in a halt loop) Bits D0-D5 are read/write and bits D6-D11 are read only. The interrupt vector provides a means for the CLB to know who caused an interrupt. This register is only accessible by the 68000. The first part of this test uses a walking '1' pattern to test each bit of the 8-bit interrupt vector register and the lower 6- bits of the command/status register. If a pattern miscompare error is detected, the expected and actual values are returned along with a status value indicating the defective register. The address of the defective register is also returned. FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Pa t turns off this hardware refresh and relies on a precisely controlled software refresh for testing purposes. A total of 256 RAS cycles (each refreshing a 256 byte block) are needed within a 2ms period to refresh the entire memory. This test writes each 'block' with the byte value '55' and immediately after the last write (which refreshed the entire block) a precise 2ms timing period is entered. Part of this period is used to write the next block. After 2ms the first location is tested for fading (this read refreshes the entire block), followed by the rest of the block in succession. This algorithm is repeated in succession for all 256 blocks covering the low and high windows. Upon successful completion of this entire pass the test is repeated FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 8 using the inverted pa ge 7 The following error codes are returned: VECTERR 200 VECTOR REG RD/WR ERROR CMDSERR 201 CMD/ST REG RD/WR ERROR The second part of this test reads command/status register bits D6-D11 and tests for a possibly incorrect power-up/reset initialization. The correct initialization is as follows: D6 Ack. Int.(to CLB) (1 => no acknowledge interrupt pending) D7 Attn. Int.(to CLB) (1 => no attention interrupt pending) D8 Expansion ID 1 (1 => floating input or 0 indicates a piggyback expansion board installed) D9 Expansion ID 2 (1 => floating input or 0 indicates a piggyback expansion board installed) D10 Latched NMI (0 => no parity error) D11 Z80 Halt Status (1 => Z80 not halted) ttern 'aa'. Error code 1 being returned indicates a pattern miscompare error. The expected pattern will be the word value '55' or 'aa' as applicable. The failed address will be in the range 7s8000 (hex) through 7sffff (hex). This address range represents 32K bytes or 16K words, or only one window. A window code is also returned to indicate which window the error actually occurred in, "win = 0" for low window and "win = 2" for high window. The 's' in the address will be the hex value a-e depending on the slot being tested. The last value written to each byte in memory is a 76 (hex), the Z-80 halt instruction. This is for use in subsequent testing. Note that the Z-80 is held in reset for this test. _ 4. _ 4: _ The ram parity logic writes a parity bit with each byte written to the dual-port ram. When read, this p The following error codes are returned: B6RDERR 202 BIT 6 STATUS REG RD ERROR B7RDERR 203 BIT 7 STATUS REG RD ERROR BARDERR 206 BIT A STATUS REG RD ERROR BBRDERR 207 BIT B STATUS REG RD ERROR Note that bits 8 and 9 (Expansion bits) are not tested since the diagnostic software cannot know if an expansion board is installed or not. _ 3. _ 3: _ This test verifies the 64K bytes of shared memory with the DRAM refresh diasabled. The Z-80 being held in reset disallows any refresh cycles from occurring. All dynamic ram chips are tested for their ability to not fade with refresh withheld for a 2ms period. The COMB board multiplexes address lines a8-a15 for a hardware RAS-only refresh. This tes arity bit is checked and if a parity error occurs, indicating either a hard or soft error, two actions take place: o A non-maskable interrupt is sent to the Z-80 o The NMI flag is set in the CLB command/status register To facilitate the testing of this logic there exists the ability, via a software controlled bit in the CLB command/status register, to force a parity error to occur with any word read memory access. For this test the Z-80 is held in reset so that only the ability of the 68000 to force a parity error and cause the setting of the NMI flag will be tested. The scenario is as follows: The 68000 sets (active high) the the value 0001 (hex) to the word address 0. This location is then read causing a parity error to occur and the setting of the NMI flag. The 68000 then tests for this flag and if not set returns the following: flag'. If this flag is not set the 68000 then puts the Z-80 into reset, writes the value 76 (hex) to memory location 0 and again sets the 'Software Latched Reset' bit in the command/status register again taking the Z-80 out of reset. The status register is again polled and if the 'Halt Status' flag is now active the following values are returned: o The error code FOZ80HT 12 o The value of the command/status register o The command/status register address (should be 7s4006 (hex)) If the 'Halt Status' flag is still not detected after a reasonable amount of time the following values are returned: o The error code NOZ80HT 11 o The value of the command/status register o The command/status register address (should be 7s4006 (hex)) _ 6. _ 6: _ o The error code PARERR1 208 o The failed address 7s8000 (hex) o The value of the command/status register After reading the set NMI flag, the 68000 then clears the NMI flag by writing a 2 value to the Z-80 NMI command register (this register provides a means for the 68000 to force a non-maskable interrupt to the Z-80 and clear the NMI flag), and resets the 'Force Bad Parity' bit in the command/status register. The 68000 then again writes word location 0 with the value 01 and reads it back. The command/status register is then re-tested for the NMI flag and if it is still set the following values are returned: FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 9 o The error code PARERR2 209 o The failed address 7s8000 (hex) o The value of the command/status register This test verifies the 64K bytes (32K words) of shared memory. At this point in the testing sequence the Z-80 is halted and thereby refreshing itself. A walking '1', walking '0' pattern is used in the following manner: First the pattern 0101 (hex) is written, as words, to all locations in memory. Next each location is read, as bytes, compared with the expected pattern, 01 (hex), and after a successful FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 10 comparison the same byte is written with the next pattern 02 (hex). When all of memory is successfully read/rewritten, the memory is next read, as words, and compared with the expected value 0202 (hex). After each successful compare the next pattern 0404 (hex) is written to the same word. This alternating byte, word patt Before this test returns, regardless of its outcome, the value 7676 (hex) is written to memory location 0 to allow correct execution of the following test. _ 5. _ 5: _ This test verifies that the Z-80 can be started and that it can read from memory. It also indicates that the local data bus is in good shape and that the data lines are not transposed from the CLB data lines. The shared memory is first refreshed by doing 256 byte read cycles. The Z-80 reset line is then released by the 68000 setting the The Z-80 should now fetch an instruction from memory location 0. The memory is entirely filled with 'halt' instructions so that the Z-80 should immediately halt, thereby resetting the 'Z-80 Halt Status' flag (active low) in the 68000 command/status register. The 68000 then polls for the 'Z-80 Halt Status ern is continued through the walking '1' pattern, then into the walking '0' pattern. An error code of 1 returned indicates an MC68000 pattern miscompare error. Also returned are the expected pattern (byte or word as applicable), the actual value read and the failing address. The failing address will be in the range 7s8000 (hex) through 7sffff (hex) and could be a word (even only, and indicated by a word length expected value) or byte address (even or odd, and indicated by a byte length expected pattern). This address range represents 32K bytes or 16K words, or only one window. A window code is also returned to indicate in which window the error actually occurred in, "window = 0" for low window and "window = 2" for high window. The 's' in the address will be the hex value a-e depending on the slot being tested. The last value written to each byte in memory is a 76 (hex) the Z-80 halt i r to 1 then executes the instruction (a halt). The pc value is stacked high byte first which accounts for the reverse order. The search is necessary because the stack pointer register powers up in a random state and the reset does not alter this fact. The search is started at the top of memory though because this register tends to (non-randomly) prefer the upper half of memory. If the pc value is not found the following information is returned: o The error code NOPCVAL 211 o The value of the command/status register o The command/status register address (should be 7s4006 (hex)) _ 8. _ 8: _ This test verifies the functionality of the COMB refresh logic. After a long (~3s) delay, with the Z-80 still in its halted state after the successful execution of the previous test, t nstruction. This is for use in subsequent testing. _ 7. _ 7: _ This test is a repeat of Test 1.4 but since the Z-80 is now in a halted state a forced parity error as described earlier will cause a non-maskable interrupt to the Z-80. The test proceeds as follows: The 68000 sets (active high) the Force Bad Parity bit in its command/status register. It then writes the value 0001 (hex) to the word address 00c8 (hex). This was an arbitrary selection. This location is then read causing a parity error to occur. This causes the NMI flag to be set in the 68000 command/status register and a non-maskable interrupt to be received by the Z-80. The Z-80 will be forced to stack its program counter value and jump to memory location 0066 (hex) to fetch an instruction. Since the memory is filled with halt instructions the Z-80 should immediately halt. The memory is again searched for the stacked program counter value 0100 (hex) or 0076 then 7601 as previously described. Since the refresh cycle continues to occur during the halted state no memory degradation should have occurred. If the program counter value is not found the error code: NOPCVAL 211 is returned along with the command/status register address and its contents. NOTE: This test is dependent on the correct execution of test 1.7. If a failure occurs tests 1.1 through 1.7 will need to be rerun and correctly executed. FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 12 _ 4. _ The Z-80 based tests are executed with the 68000 as overseer. The very-low level tests (as Z-80 executable code) are written to the dual-port memory on a word basis sta 68000 then tests for the NMI flag to be set and if not set returns the following values: o The error code PARERR3 210 o The value of the command/status register o The command/status register address (should be 7s4006 (hex)) If the NMI flag is set as expected the 68000 then performs a memory search starting at the top of memory for the program counter value of 0100 (hex). The actual search is for either 0100 or 0076 then 7601 using a high to low memory search. The different possibilities occur because the stack pointer register could power-up in either an odd or even state. The 0100 (hex) pc value occurs because after the reset is pulled the Z80 fetches an FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 11 instruction from location 0, increments the program counte rting at location 0. When the instructions from location 0. After the initial tests insure basic system integrity, the higher-level Z-80 tests are loaded into the dual-port memory, again starting at location 0, from Intel hex format record files. Throughout these tests, after the 68000 down-loads the Z-80 program and releases the reset, it polls the 'Halt Status' flag for a Z-80 halted condition, this being the means for the Z-80 to indicate the completion of a particular test. Before halting the Z-80 also writes test status information into reserved memory locations which the 68000 can then access. The Z- 80 is given a sufficient amount of time for test completion but if the halt condition isn't achieved in a reasonable time the 68000 will first try and force the Z-80 to halt which would yield the common error code: FOZ80HT 12 as indicated previously or the error code: NOZ80HT 11 if the Z-80 can not be h Pattern Miscompare Z80P1E6 25 PASS 1, Z-80 Command/Status Pattern Miscompare Z80P2E1 26 PASS 2, CTC Channel 0 Pattern Miscompare Z80P2E2 27 PASS 2, CTC Channel 1 Pattern Miscompare Z80P2E3 28 PASS 2, CTC Channel 2 Pattern Miscompare Z80P2E4 29 PASS 2, CTC Channel 3 Pattern Miscompare Z80P2E5 30 PASS 2, SIO Channel B Pattern Miscompare The Z-80 Command/Status register cannot be reread (at least not with valid data) on pass 2 because this register is affected by the software latched reset. If a four-port Comm 'B' communications adapter is installed, ad alted. _ 1. _ 1: _ This lowest level Z-80 test determines if the lower 6 address lines are valid. Also further tested are the Z-80 data lines and the ability to talk to the CTC, SIO, and Z-80 command/status register chips. This is accomplished with the use of I/O read/write instructions to all four channels of the Counter Timer chip, channel 'B' of the Serial I/O chip, and the Z-80 command/status register. The following algorithm is used: A walking '1' test pattern is used for the 6 accessible I/O locations. The location's pattern is written then read back and stored in memory location 0001 (hex). The processor then halts and control returns to the 68000, which accesses memory location 0001 (hex) and tests for the correct pattern. This back-and-forth scheme is repeated for all six locations. Upon successful com ding two asyncronous ports and a CTC chip, additional testing will automatically occur and the following error codes will apply: Z80P3E1 32 PASS 3, CTC Channel 4 Pattern Miscompare Z80P3E2 33 PASS 3, CTC Channel 5 Pattern Miscompare Z80P3E3 34 PASS 3, CTC Channel 6 Pattern Miscompare Z80P3E4 35 PASS 3, CTC Channel 7 Pattern Miscompare Z80P3E5 36 PASS 3, SIO Channel D Pattern Miscompare Z80P4E1 38 PASS 4, CTC Channel 4 Pattern Miscompare Z80P4E2 39 PASS 4, CTC Channel 5 Pattern Miscompare Z80P4E3 40 PASS 4, CTC Channel 6 Pattern Miscompare Z80P4E4 41 PASS 4, CTC Channel 7 pletion the second part begins by simply reading each location, again writing the value to memory location 0001 (hex) and returning control to the 68000. A pattern miscompare at this point then is an indication of an address line interaction problem. The following error codes are returned: FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 13 Z80P1E1 20 PASS 1, CTC Channel 0 Pattern Miscompare Z80P1E2 21 PASS 1, CTC Channel 1 Pattern Miscompare Z80P1E3 22 PASS 1, CTC Channel 2 Pattern Miscompare Z80P1E4 23 PASS 1, CTC Channel 3 Pattern Miscompare Z80P1E5 24 PASS 1, SIO Channel B Pattern Miscompare Z80P4E5 42 PASS 4, SIO Channel D Pattern Miscompare FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 14 Additional error information returned are the expected pattern value, the actual pattern, and the address of memory location 0. Note that the expected pattern will be the word length value 3exx (hex) where xx is the appropriate walking '1' pattern and the '3e' represents a Z-80 Load register A instruction (which is the first instruction executed in every case). The address of memory location 0 should be 7s8000 (hex) where the s indicates the slot being tested: 'a-e'. _ 2. _ 2: _ This test expands on the previous test with the verification of the upper 10 Z- non 0x00). 7 18 0x55 0x1ff Loc. '3f' tested for any interaction (ie non 0x55). 8 17 0x55 0x200 Loc. '0' tested for any interaction (ie non 0x00). 9 17 0x55 0x3ff Loc. '3f' tested for any interaction (ie non 0x55). 10 16 0x55 0x400 Loc. '0' tested for any interaction (ie non 0x00). 11 16 0x55 0x7ff Loc. '3f' tested for any interaction (ie non 0x55). 12 15 0x55 0x800 Loc. '0' tested for any interaction (ie non 0x00). 13 15 0x55 0xfff Loc. '3f' tested for any interaction (ie non 0x55). 14 14 0x55 0x1000 Loc. '0' tested f 80 address lines. In order to allow testing of address lines 6-15 the code requires less than 64 bytes. The test uses a probe method for sequential address line verification as follows: Memory location 0000 (hex) is written with a 00 (hex) pattern. Memory location 003f (hex) is written with a 55 (hex) pattern then verified. Location 0040 (hex) is then written with the 55 (hex) pattern and location 0000 (hex) is tested for any interaction, or non-zero value. Next location 007f (hex) is written with the 55 (hex) pattern and location 003f (hex) is tested for any interaction, or non-55 (hex) value. This method is successively used through the final probe address' 8000 (hex) and ffff (hex) being tested for interaction with locations 0000 (hex) and 003f (hex) respectively. Upon successful completion the test repeats, using the inverted test pattern information for correct troubleshooting: or any interaction (ie non 0x00). 15 14 0x55 0x1fff Loc. '3f' tested for any interaction (ie non 0x55). 16 13 0x55 0x2000 Loc. '0' tested for any interaction (ie non 0x00). 17 13 0x55 0x3fff Loc. '3f' tested for any interaction (ie non 0x55). 18 12 0x55 0x4000 Loc. '0' tested for any interaction (ie non 0x00). 19 12 0x55 0x7fff Loc. '3f' tested for any interaction (ie non 0x55). 20 11 0x55 0x8000 Loc. '0' tested for any interaction (ie non 0x00). 21 11 0x55 0xffff Loc. '3f' tested for any interaction (ie non 0x55). FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 15 Error Loop Test Probe Number Count Pattern Address Particular Test 1 20 0x55 0x3f Loc. '3f' tested for '55' 2 20 0x55 0x40 Loc. '0' tested for any interaction (ie non 0x00). 3 20 0x55 0x7f Loc. '3f' tested for any interaction (ie non 0x55). 4 19 0x55 0x80 Loc. '0' tested for any interaction (ie non 0x00). 5 19 0x55 0xff Loc. '3f' tested for any interaction (ie non 0x55). 6 18 0x55 0x100 Loc. '0' tested for any interaction (ie 22 10 0xaa 0x40 Loc. '0' tested for any interaction (ie non 0x00). 23 10 0xaa 0x7f Loc. '3f' tested for any interaction (ie non 0x55). 24 9 0xaa 0x80 Loc. '0' tested for any interaction (ie non 0x00). 25 9 0xaa 0xff Loc. '3f' tested for any interaction (ie non 0x55). 26 8 0xaa 0x100 Loc. '0' tested for any interaction (ie non 0x00). FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 16 27 8 0xaa 0x1ff Loc. '3f' tested for any interaction (ie non 0x55). 28 7 0xaa 0x200 Loc. '0' tes The successful execution of this test ensures that no Dual- Port ram contention problems exist. The test begins with the 68000 down-loading the Z-80 executable program. The 'Software Latched Reset' is then pulled and the Z-80 begins program execution. The stack pointer is set to fffe (hex) and the Z-80 begins testing memory from location 0284 (hex) to 0f80 (hex). This upper figure is to ensure sufficient stack area. A walking '1', walking '0' test pattern is used by the Z-80. While this is going on While this is going on the 68000 enters a loop which first tests for the 'Halt Status' flag (which indicates Z-80 test completion) then enters a memory test routine on memory locations 0278 through 0280 (hex). The test patterns 55 and aa (hex) are used. Upon successful completion of this portion of the loop the 68000 then scans the memory area that the Z-80 is testing at the same time, 0284 t ted for any interaction (ie non 0x00). 29 7 0xaa 0x3ff Loc. '3f' tested for any interaction (ie non 0x55). 30 6 0xaa 0x400 Loc. '0' tested for any interaction (ie non 0x00). 31 6 0xaa 0x7ff Loc. '3f' tested for any interaction (ie non 0x55). 32 5 0xaa 0x800 Loc. '0' tested for any interaction (ie non 0x00). 33 5 0xaa 0xfff Loc. '3f' tested for any interaction (ie non 0x55). 34 4 0xaa 0x1000 Loc. '0' tested for any interaction (ie non 0x00). 35 4 0xaa 0x1fff Loc. '3f' tested for any interaction (ie non 0x55). hrough f800 (hex), and compares the value read at each location with each of the 16 possible patterns the Z-80 test uses. Upon successful completion of this scan the loop repeats. The timing is such that 4 of these 68000 loops are executed before the FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 17 Z-80 memory test completes and the Z-80 halts. If the Z-80 or 68000 detect a memory error the following error information is returned: o The error code M68PATM 1 (68000 detects a miscompare) o The error code Z80PATM 2 (Z-80 detects a miscompare) o The actual value read from the memory byte or word accessed o The expected pattern written to memory (byte or word) o The error address If the error occurred during the Z-80 memory scan portion of the 68000 loop the error address i 36 3 0xaa 0x2000 Loc. '0' tested for any interaction (ie non 0x00). 37 3 0xaa 0x3fff Loc. '3f' tested for any interaction (ie non 0x55). 38 2 0xaa 0x4000 Loc. '0' tested for any interaction (ie non 0x00). 39 2 0xaa 0x7fff Loc. '3f' tested for any interaction (ie non 0x55). 40 1 0xaa 0x8000 Loc. '0' tested for any interaction (ie non 0x00). 41 1 0xaa 0xffff Loc. '3f' tested for any interaction (ie non 0x55). Along with each error code returned is the actual pattern read. _ 3. _ 3: _ s returned along with the actual pattern read. Since there are 16 possible expected values nothing is returned in this instance. _ 4. _ 4: _ This test verifies that the interrupt handshake logic is functional. Two groups of sub-tests are executed as follows: Group 1: o Z-80 sets MC68000 interrupt with-out enable. o Z-80 sets MC68000 acknowledge with-out enable. o MC68000 sets Z-80 interrupt with-out enable. o MC68000 sets Z-80 acknowledge with-out enable. Group 2: o MC68000 sets Z-80 interrupt with enable. Before describing these tests a brief introduction will be given to the 68000 to Z-80 interrupt structure. The Z-80 uses the CTC chip, channel 2 as the means to detect these interrupts, if it wishes to enable them. It does this by setting up c rrupt flag. If it is not active the error code: NO68AT 400 is returned along with the 68000 command/status register address and contents. The second test begins with the 68000 again writing a small program to the dual-port memory starting at location 0. The 'Software Latched Reset' bit is then set, the 68000 touches the CLB Clear Attention and CLB Clear Acknowledge registers to insure a known state and the reset is pulled. The Z-80 should then immediately set the 68000 acknowledge by writing the value 06 (hex) to the Z-80 command/status register (I/O address bc (hex)). The 68000 command/status register was previously written with both the CLB Attention mask set (Interrupt disabled) and the CLB Acknowledge mask set (Acknowledge disabled) so that the 68000 is not interrupted. The Z-80 then halts. After a small software delay the 68000 tests for the CLB Acknowledge Interrupt flag. If it hannel 2 in counter mode, the time constant register set to 1, and active high triggering. With channel 2 interrupts enabled and a vector previously written to channel 0, the CTC is ready. Prior to getting a 68000 interrupt though the Z-80 must execute several instructions to initialize itself. The Z-80 'i' register must be written with the upper byte address of the interrupt table, the interrupt mode 2 instruction (IM 2) must be executed and finally the enable interrupt instruction (EI) is executed. Also the actual interrupt handler routine must have previously been written at the location indicated by the interrupt table address. Either interrupt to the Z-80 causes the CTC down-counter to decrement and reaching 0 an interrupt is sent to the Z-80. Using the Zilog interrupt mode 2 scheme the CTC is the highest priority interrupting device to the Z-80. The first test begins with the 68000 writ is not active the error code: NO68AK1 401 is returned along with the 68000 command/status register address and contents. The third test is more involved with the 68000 writing a polling program to the dual-port memory starting at memory location 0. The same procedure as Test 2 is again performed with the 'Software Latched Reset' being set, the 68000 then touches the CLB Clear Attention and CLB Clear Acknowledge registers to insure a known state and the reset is pulled. This test does not fully enable the 68000/Z-80 interrupt scheme described earlier. Instead, the CTC channel 2 time constant register is initialized with a value of 2 and the Z-80 command/status register is polled for the 68000 attention interrupt. The 68000 delays slightly before writing to the CLB Set Attention register. This is necessary to allow the Z-80 sufficient time to set up the CTC and begin it ing a small program to the dual-port memory starting at location 0. The 'Software Latched Reset' bit is then set, the 68000 touches the CLB Clear Attention and CLB Clear Acknowledge registers to insure a known FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 18 state, (the reset does not insure a known state for these two signals) and the reset is pulled. The Z-80 should then immediately set the 68000 interrupt by writing the value 05 (hex) to the Z-80 command/status register (I/O address bc (hex)). The 68000 command/status register was previously written with both the CLB Attention mask set (Interrupt disabled) and the CLB Acknowledge mask set (Acknowledge disabled) so that the 68000 is not interrupted. The Z-80 then halts. After a small software delay the 68000 tests for the CLB Attention Inte s polling routine. If after a reasonable amount of time the 68000 interrupt is not detected, the Z-80 writes an error code to memory location 0 and halts. If the interrupt is detected the Z-80 reads the CTC channel 0 down-counter register to verify that the decrement to 1 occurred correctly. If the value read is not a 1 an error code is written to memory location 0 and the Z-80 halts. If the test is correctly executed the Z-80 simply halts. The 68000 polls for the 'Halt Status' flag during this time and upon its reception tests memory location 0 for the Z-80 completion status. The following error codes are returned: Z80TCE1 7 Z80 Time Constant Decrement Error Z80TOE1 8 Z80 Time Out Error FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 19 Also returned in the event of an error are the sets the CLB Acknowledge flag so that upon detecting the 'Halt Status' flag from the Z-80 the 68000 then tests to make sure the Z-80 correctly acknowledged its interrupt. The Z- 80 interrupt handler routine writes an error code to memory location 0 if it does not see the Z-80 attention flag (ie the interrupt occurred but that portion of the circuitry which sets the Z-80 status register bit is inoperative) and also if after issuing a Z-80 Clear Attention (writing a 0x6 to I/O port 0xbc) the bit wasn't cleared. The Z-80 will also return a time-out error code if after a reasonable amount of time the interrupt does not occur. These codes are as follows: Z80TOE3 108 Z80 Time Out Error NOZ80AT 109 No Z80 Attn. Interrupt seen in the Interrupt handler NOATNCL 110 Z80 Attn. Interrupt wasn't cleared in the Interrupt handler FORTUNE SYSTEMS CONFIDENTIAL No 68000 command/status register address and its contents. The fourth test is identical to the third except that the 68000 sets the Z-80 Acknowledge Interrupt. The error codes returned are: Z80TCE2 17 Z80 Time Constant Decrement Error Z80TOE2 18 Z80 Time Out Error Also returned are the 68000 command/status register address and contents. The final test has the 68000 setting a Z-80 Attention Interrupt as in the third test but with the Z-80 fully enabled for interrupt mode 2 response. This test requires a program written to the dual-port memory starting at location 0. The interrupt handler routine is written to memory beginning at location 002d (hex) so that the address written to the interrupt table address 0064 (hex) is 002d (hex). The Z-80 'i' register is cleared to 0 upon reset and is left that way. The vector written to CTC channel 0 (CTC programming vember 14, 1983 COMM-B Test Implementation Documentation Page 20 If the 68000 does not see the CLB Acknowledge Interrupt flag it returns the error code: NO68AK2 402. Also returned with any error code is the 68000 command/status register address and its contents. _ 5. _ 5: _ This test consists of three parts: o Part 1 writes and reads all accessible registers in the Counter Timer and Serial I/O chips with a walking '1' pattern and its inverse. o Part 2 tests each CTC channel using a timer mode algorithm. o Part 3 tests SIO channels 'A' and 'B' using one of two user selectable data loop-back methods. The final 2 parts are implemented using the Z-80 vectored interrupt mode 2. For part 1 the 68000 down-loads the Z-80 executable requirement) is 60 (hex). The low-order nibble value 4 in the interrupt vector table is part of the interrupt mode 2 response in the CTC with the 4 indicating a channel 2 interrupt (a single vector can thus represent all four channels). After loading the dual-port memory and pulling the reset flag, the 68000 then sets the Z-80 interrupt and begins polling the Z-80 'Halt Status' flag which indicates Z-80 test completion. The Z-80 should have been immediately interrupted when the CTC down-counter reached zero with the Z-80 vectoring to the interrupt handler routine. At this point the Z-80 does not know which of the 68000 interrupts (Attention or Acknowledge) caused the interrupt so it must read its status register to verify which interrupt occurred (it tests the Z-80 Attention flag in this case) and then clears the Attention flag by writing a value 0x6 to I/O port 0xbc. This clearing automatically program to the dual-port memory starting at location 0. The Z-80 reset is latched then released. The 68000 then begins a software delay, monitoring the 'Halt Status' flag while the Z-80 proceeds with the following algorithm: o The pattern 01 (hex) is written to CTC channel 0 then read back. o This actual value is then compared with the expected value and if a pattern miscompare is detected the Z-80 writes a specific error code, the actual value read, and the expected value to memory before halting. o These values are then retrieved by the 68000 and returned with the error status. o If no error occurs the inverse pattern 0xfe is written to the CTC channel 0 time constant register and the test sequence is repeated. o The test then proceeds with testing channels 1, 2, and 3 then SIO cha CTC Ch.5 Time Constant Pattern Miscompare Error E25Z045 45 CTC Ch.5 Inverted Time Const Pattern Miscompare Error E25Z046 46 CTC Ch.6 Time Constant Pattern Miscompare Error E25Z047 47 CTC Ch.6 Inverted Time Constant Pattern Miscompare Error E25Z048 48 CTC Ch.7 Time Constant Pattern Miscompare Error E25Z049 49 CTC Ch.7 Inverted Time Constant Pattern Miscompare Error E25Z050 50 SIO Ch.D Interrupt Vector Pattern Miscompare Error E25Z051 51 SIO Ch.D Inverted Int. Vector Pattern Miscompare Error In Part 2 each CTC channel is tested in the timer mode using the Zilog vectored interrupt mode 2. Specifically, first an nnel 'B' read/write register 2. o Each is tested with the pattern 0x01 and its inverse. o The test pattern is then left-shifted and the cycle repeats itself through the final pattern of 80 (hex) and its inverse 7f. The following error codes are returned: FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 21 E25Z032 32 CTC Ch.0 Time Constant Pattern Miscompare Error E25Z033 33 CTC Ch.0 Inverted Time Constant Pattern Miscompare Error E25Z034 34 CTC Ch.1 Time Constant Pattern Miscompare Error E25Z035 35 CTC Ch.1 Inverted Time Const Pattern Miscompare Error E25Z036 36 CTC Ch.2 Time Constant Pattern interrupt service routine is written to memory location 0x1000, then Z-80 executable code is down-loaded beginning with memory location 0. The 68000 then resets the Z-80 then releases it. The Z-80 then initializes the particular CTC channel it is testing. FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 22 This initialization puts the channel into the timer mode, loads the time constant register with the decimal value 225, and enables the channel interrupts. A vector value of 0xf8 is also written. The Z- 80 has previously initialized the 'i' register with the value 0x01. It now executes the instructions IM 2 and EI, loads the accumulator with the decimal value 211 and enters a very tight (ie calculated) loop which loads memory location 0x2000 with the accumulator value, decrements the accumulator, and tests it Miscompare Error E25Z037 37 CTC Ch.2 Inverted Time Constant Pattern Miscompare Error E25Z038 38 CTC Ch.3 Time Constant Pattern Miscompare Error E25Z039 39 CTC Ch.3 Inverted Time Constant Pattern Miscompare Error E25Z040 40 SIO Ch.B Interrupt Vector Pattern Miscompare Error E25Z041 41 SIO Ch.B Inverted Int. Vector Pattern Miscompare Error If a four-port Comm 'B' communications adapter is installed its DART and CTC chip will be tested also with the following error codes returned: E25Z042 42 CTC Ch.4 Time Constant Pattern Miscompare Error E25Z043 43 CTC Ch.4 Inverted Time Constant Pattern Miscompare Error E25Z044 44 for zero. If the accumulator value does reach zero, indicating an interrupt never occurred the Z-80 writes a specific error code to memory and halts. Otherwise the loop-back process should have occurred exactly 111 times resulting in the value 100 written to memory location 0x2000 when the interrupt occurs. The interrupt then causes the Z-80 to vector to the interrupt routine which simply issues a channel reset to the particular channel being tested, writes a completion status value to a particular memory location which the 68000 can access, then halts. After detecting the Z-80 halt status the 68000 then tests for the correct Z-80 completion status and the correct value (100 +- 1) read from memory location 0x2000. This algorithm is repeated for all four channels and the following error codes are possible: CTC0E00 3 CTC Ch.0 No CTC Interrupt (Z-80 Timeout) CTC0E01 S-232 connector pins 2 and 3 for each channel tested. Four separate tests are used for each channel, with configuration as follows (Channel 'A' uses CTC channel 0 and Channel 'B' uses CTC channel 1 for baud rate generation): Test 1: Clock mode X16, 1 stop bit, even parity 8 bits/char TX, 8 bits/char RX CTC: Time Constant = 18 Timer mode, Prescaler X16 Test 2: Clock mode X32, 2 stop bits, odd parity 7 bits/char TX, 7 bits/char RX CTC: Time Constant = 72 Counter mode Test 3: Clock mode X64, 1.5 stop bits, no parity 8 bits/char TX, 8 bits/char RX CTC: Time Constant = 9 Counter mode Test 4: Clock mode X1, 1 stop bit, even parity 8 bits/char TX, 8 bits/char RX 13 CTC Ch.0 Loop Count Error (0x2000 != 100+-1) CTC1E00 4 CTC Ch.1 No CTC Interrupt (Z-80 Timeout) CTC1E01 14 CTC Ch.1 Loop Count Error (0x2000 != 100+-1) CTC2E00 5 CTC Ch.2 No CTC Interrupt (Z-80 Timeout) CTC2E01 15 CTC Ch.2 Loop Count Error (0x2000 != 100+-1) CTC3E00 6 CTC Ch.3 No CTC Interrupt (Z-80 Timeout) CTC3E01 16 CTC Ch.3 Loop Count Error (0x2000 != 100+-1) If a four-port Comm 'B' communications adapter is installed its CTC chip will be tested also with the following error codes returned: CTC4E00 7 CTC Ch.4 No CTC Interrupt (Z-80 Timeout) CTC4E01 17 CTC Ch.4 Loop Count Error (0x2000 != 100+-1) CTC5E00 8 CTC Ch.5 No CTC Interrupt (Z-80 Timeout) CTC5E01 18 CTC Ch.5 Loop Count Error (0x2000 != 100+-1) CTC6E00 9 CTC Ch.6 No CTC Interrupt (Z-80 Timeout) CTC6E01 19 CTC CTC: Time Constant = 13 Timer mode, Prescaler X256 Before test execution begins the 68000 writes the interrupt handler routine address' to the interrupt table memory locations as indicated: Memory Location Routine Address Description 0x314 0x320 SIO Ch.'B' Receive Character Routine 0x316 0x32a SIO Ch.'B' Special Receive Condition 0x31c 0x34b SIO Ch.'A' Receive Character Routine 0x31e 0x355 SIO Ch.'A' Special Receive Condition The actual interrupt routines are next written to memory at the specified address'. The SIO 'Status Effects Vector' bit is the software means for the SIO to support the Z-80 Interrupt Mode 2 vectored interrupt response structur Ch.6 Loop Count Error (0x2000 != 100+-1) CTC7E00 10 CTC Ch.7 No CTC Interrupt (Z-80 Timeout) CTC7E01 20 CTC Ch.7 Loop Count Error (0x2000 != 100+-1) Along with the particular loop count error code returned the address of location 0x2000 is returned (should be 7sa000, where s = a-e is the slot being tested) along with the actual value read and the expected value (100). The Part 3 tests are used to verify the ability of SIO channels 'A' and 'B' to operate in the asyncronous mode. This is accomplished using both internal and external loop-back methods. FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 23 The internal method is the default test with the external method requiring the execution of the (e)xternal command and the use of the Special Test Fixture connector for the connection of R e. Also required to support this response is the interrupt vector value 0x10 written to SIO channel 'B' read/write register 2 as part of the initialization sequence for each test ('A' or 'B'). Each test begins with the 68000 down-loading the Z-80 code, setting the 'Software Latched Reset' then immediately resetting it. The Z-80 then begins its program execution with the initialization of the required CTC channel. CTC channels '0' and '1' are used for SIO channels 'A' and 'B' baud rate generation respectively. The FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 24 system clock is used as the clock/trigger input to these channels. The Z-80 then initializes the particular SIO channel being tested with the required test parameters as described above, sets Transmit Enable, Receive Enable, sets the Special Effects Vector bi el A Parity Error SIOBER1 139 SIO Channel B Test 1 Error SIOBER2 140 SIO Channel B Test 2 Error SIOBER3 141 SIO Channel B Test 3 Error SIOBER4 142 SIO Channel B Test 4 Error SIOBFER 143 SIO Channel B Framing Error SIOBOER 144 SIO Channel B Overrun Error SIOBPER 145 SIO Channel B Parity Error If a four-port Comm 'B' communications adapter is installed the two additional asyncronous ports and CTC chip will only be tested if the external loopback command 'e' is used. In that case the part 3 tests just described will be executed and the following error codes returned: FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 25 SIOCER1 146 SIO Channel C Test 1 Error SIOCER t and finally sets the Interrupt response for Interrupt on first Rx character and all Rx characters thereafter. Note that since the test algorithm will use a timed loop method for individual character transmission the transmit interrupt enable bit is not set. The Z-80 then completes the Interrupt Mode 2 response setup with the execution of instructions to load the 'i' register with the value 0x03, set IM 2 and then enable interrupts, EI. The actual testing will now commence with the Z-80 writing the character string "FORTUNE 32:16", one character at a time, to memory location 0x2000. This occurs in a transmit loop such that after the character transmission occurs the Z-80 begins a software delay sufficient (if the hardware is good) to allow a Rx interrupt to occur. The Z-80 then (via the IM 2 response scheme) vectors to the correct interrupt handler routine (Ch.'A' or 'B'), reads the 2 147 SIO Channel C Test 2 Error SIOCER3 148 SIO Channel C Test 3 Error SIOCER4 149 SIO Channel C Test 4 Error SIOCFER 150 SIO Channel C Framing Error SIOCOER 151 SIO Channel C Overrun Error SIOCPER 152 SIO Channel C Parity Error SIODER1 153 SIO Channel D Test 1 Error SIODER2 154 SIO Channel D Test 2 Error SIODER3 155 SIO Channel D Test 3 Error SIODER4 156 SIO Channel D Test 4 Error SIODFER 157 SIO Channel D Framing Error SIODOER 158 SIO Channel D Overrun Error SIODPER 159 SIO Channel D Parity Error The Part 4 tests are used to verify the sync/async clock circuitry for SIO channel's 'A' and 'B' and the various modem control lines used by the SIO and DART (if the optional 4-port com character just transmitted and then writes it to memory location 0x2000. The routine then enables interrupts and returns. The delay then completes and the Z-80 then compares the character just transmitted with the value written to location 0x2000. This method is repeated until the entire string has been transmitted. If an incorrect compare takes place a unique (to the particular test) error code is returned along with the expected character value (ascii value) and the actual value read. The following error codes are returned: SIOAER1 132 SIO Channel A Test 1 Error SIOAER2 133 SIO Channel A Test 2 Error SIOAER3 134 SIO Channel A Test 3 Error SIOAER4 135 SIO Channel A Test 4 Error SIOAFER 136 SIO Channel A Framing Error SIOAOER 137 SIO Channel A Overrun Error SIOAPER 138 SIO Chann adapter is installed). This testing is accomplished only with the (e)xternal command having been executed and the correct Special Test Fixture installed. The ability to select from asyncronous internally generated clocks or syncronous externally generated clocks is first tested on SIO channel's 'A' and 'B'. Syncronous clocking is selected by asserting bit '6' for channel 'A' and bit '5' for channel 'B' in the Z-80 Command/Status register. The loop-back test fixture is installed with pins 24 (maintenance clock), 15 (transmit clock), and 17 (receive clock) tied together. The maintenance clock is just the particular channel's asyncronous clock from its dedicated CTC channel. Part 3 test 1 is then repeated for each channel with the following error codes returned: MODAER1 160 Channel A Sync Clock Error MODBER1 170 Channel B Sync Clock Error The functiona MODBER8 177 Channel B AutoEn loop-back Error If a four-port Comm 'B' communications adapter is installed this test will be repeated with the only difference being that RS- 232 pin 6 connects to the RI (ring indicator) pin on the DART. The following error codes are returned: MODCER1 180 Channel C CTS not low MODCER2 181 Channel C DCD not low MODCER3 182 Channel C RI not low MODCER4 183 Channel C CTS not high MODCER5 184 Channel C DCD not high MODCER6 185 Channel C RI not high MODCER7 186 Channel C AutoEn loop-back Error MODDER1 190 Channel D CTS not low MODDER2 191 Channel D DCD not low MODDER3 192 Channel D RI not low MODDER4 193 Channel D CTS not high MODDER5 194 Channel D DCD not high lity of the modem control lines is next tested. For SIO channels 'A' and 'B' the DTR (data terminal ready) line (pin 20) is tied together with the DCD (data carrier detect) line (pin 8) and the DSR (data set ready) line (pin 6). Also the RTS (ready to send) line (pin 4) is tied to the CTS (clear to send) line (pin 5). The test first determines that DCD, CTS, and DSR (this bit is accessed via the Z-80 Command/Status register) are in their deasserted states then procedes with initializing the SIO channel for Part 3, Test 1 with the additional assertion of the DSR and RTS bits and the assertion of the auto enables bit. The DCD, CTS, and DSR are then tested for their correct asserted values. The data loop-back test of Part 3, Test 1 is then run. With the assertion of the auto enables bit the active CTS bit enables data transmission and the assertion of the DCD bit enables data reception. This al MODDER6 195 Channel D RI not high MODDER7 196 Channel D AutoEn loop-back Error FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 lows further testing of the SIO internal FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 COMM-B Test Implementation Documentation Page 26 circuitry. The following error codes are returned: MODAER2 161 Channel A CTS not low MODAER3 162 Channel A DCD not low MODAER4 163 Channel A DSR not high MODAER5 164 Channel A CTS not high MODAER6 165 Channel A DCD not high MODAER7 166 Channel A DSR not low MODAER8 167 Channel A AutoEn loop-back Error MODBER2 171 Channel B CTS not low MODBER3 172 Channel B DCD not low MODBER4 173 Channel B DSR not high MODBER5 174 Channel B CTS not high MODBER6 175 Channel B DCD not high MODBER7 176 Channel B DSR not low PIO TEST IMPLEMENTATION DOCUMENTATION (RELEASE 1.1) Pat Harris Fortune Systems Corporation 101 Twin Dolphin Drive Redwood City, Ca. 94065 _ Diagnostic documentation on PIO tests. Fortune Systems Internal Confidential. Distribution: Pat Patrick Dennis Moore Peter Chen Darryl Phillips Cal Eberle Lee Morse John Olney Don Witt Wayne Painter Pradip Morparia Randy McDonald November 14, 1983 PIO TEST IMPLEMENTATION DOCUMENTATION (RELEASE 1.1) Pat Harris Fortune Sy (ddress)......arg1-arg5 are the option slots to test: abcde if no arg, selects slot 'B' to be tested c(ount)........arg1 is the number of times to repeat each test d(isplay)......prints all currently selected options e(nable).......parallel port testing -e(nable)......disables parallel port testing g(o)...........executes selected tests l(oop).........if arg1 is 'e', sets test to loop on first error 'a' sets selected test(s) to loop till killed 'f' arg sets selected test(s) to loop till first error -l(oop)........turns off loop mode p(ause)........on any error untill the space bar is pressed -p(ause).......turns off pause on error mode q(uit).........exits to boot prompt ':' t(est).........arg(s) select specific tests to be run use stems Corporation 101 Twin Dolphin Drive Redwood City, Ca. 94065 _ 1. _ The PIO stand-alone test and verification package provides a means to test major hardware components on up to four PIO boards simultaneously. Menu-driven to allow a wide range of user interaction, the tests provide help for the user to isolate hardware faults quickly and easily. The tests are broken up into 2 sections: MC68000 Hosted tests and combined MC68000/IOP(MC68000 I/O Processor) Hosted tests. The CLB-based tests build in complexity as the level of hardware confidence increases, while the IOP-based tests can be run independently of each other. Error information is provided as an aid to trouble-shooting and pass count and error logging is used for long-term testing and error analysis. Menu commands are provided to arg-arg for a range of tests to be run if no arg, prints description of all tests and selects to run all tests. Enter test #'s '1-f'(hex) Typing 'g' at this point will begin test execution using the following default values: o Option Slot 'B' will be tested o All tests will be run o The repeat count set to 1 o Loop mode diasabled o Pause on error disabled o Parallel Port testing disabled This test parameter information will be displayed by typing 'd'. These default values can be changed using the various commands described below. The test command 't' allows the selection of a particular test or range of tests to be run. If the following command line is entered; "t " with no arguments, all tests will be selected to be run and the following information displaye allow testing flexibility. These include a repeat count feature for extended testing and burn-in, the ability to pause on each error, and several looping modes. _ 2. _ In order to provide a minimum of difficulty in utilization, the tests are menu-driven. After program boot (set Maintenance frame 'Set boot file name' parameter to fd02/pio and execute), the Help screen will appear as follows: FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 2 Standalone PIO Test & Verification package, Pre-release version 0.d 8-8-83 general command format is: [arg1] [arg2];.. Use 'HELP'.....to reprint this summary Use 'DEL'......to terminate testing after completion of the currently executing test a FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 3 1 - Test 1.1 - Self-Test Execution 2 - Test 1.2 - Interface Registers 3 - Test 1.3 - Fixed, Movable Window Circuitry 4 - Test 1.4 - Ram Test without Refresh 5 - Test 1.5 - Ram Parity Logic 6 - Test 1.6 - IOP Instruction Execution 7 - Test 1.7 - Ram Test with Refresh 8 - Test 1.8 - IOP NMI Logic 9 - Test 1.9 - Memory Fading a - Test 2.1 - IOP Address Lines b - Test 2.2 - Ram Test with CLB Accesses c - Test 2.3 - Parallel Ports d - Test 2.4 - Real-Time Clock e - Test 2.5 - Protection Circuitry f - Test 2.6 - Interrupt Handshake Logic Examples of test command usage are; "t 2a 3-5 d" which would select tests 2 through 5, a and was entered the loop till first error mode would be initiated. This provides a means to loop forever until either an error occurrs or the CANCEL/DEL key is pressed to terminate testing. The negate loop command '-l' provides a means to terminate the selected loop mode. The pause on error command 'p' allows the user to examine the error information before continuing. Hitting the space bar resumes testing. The negate pause command '-p' provides a means to terminate the pause on error mode. The count command 'c' provides the means to repeat a particular test or group of tests a selected number of times. The command will accept arguments in octal, hexadecimal, or decimal format. If no argument is used the default value of 1 is set. The count value is common to all selected PIO's. The enable parallel port testing command 'e' enables the parallel port testing to occur in t d to be run on every selected card and; "t b;g " which would select only test b (hex) and then execute the test. The address command 'a' allows the user to select a particular slot to be tested. If no arguments are used the default condition is performed with option slot 'B' selected for testing. An example of address command usage is; "a b D " which enables PIO cards in slots 'B' and 'D' to be tested. The quit command 'q' being executed results in an exit to the boot prompt ':' which then provides a means to boot another test, the standard operating system, etc. Additionally a system reset could be used at this time to allow normal system start-up. The loop command 'l' provides a means for PIO burn-in or system debug. Three loop modes are provided; loop until an error occurs, loop always, and loop on first error that occurs. Entering the command line; ests 1.2, 1.3, and 2.3. The default condition is no parallel port testing. When the enable command is executed a message will appear to the effect that all external PIO connectors must be removed for correct program execution. The user will then be ask if the special test fixture (loopback connector) will be installed. A yes or no is expected with no being the default. The answer will then provide the switch between two independent sets of parallel port testing for tests 1.2, 1.3, and 2.3. One set will provide loopback testing while the other will not. If the external connectors are not removed and any of these tests executed erroneous data will be sent to the external devices connected. The negate parallel port testing command '-e' provides a means to terminate the parallel port testing mode. FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Doc "l e;g " provides the loop on error mode to be used on the first selected test that produces an error. Its effect on test execution is such that if an error occurs on a particular test that test will be repeated as long as the error persists. Note that an intermittent failure would eventually cause termination if only one test was FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 4 selected otherwise the next selected test would be run. To break from the error looping condition the CANCEL/DEL key is pressed. If the command; "la;g " was entered the loop always mode would be initiated. This provides a means to continuously execute the selected test(s) on the selected slot(s) forever regardless of errors until the CANCEL/DEL key is pressed. If the command; "lf;g " he single bit value representing this status will be returned to avoid confusion. Inapplicable field values in an error message will always be returned with a 0 value. PARITY ERROR - This active-low bit indicates that a parity error has occurred. It should power-up in the high state. Error message: stat= 1 adr= 7X4150 exp= 1 act= 0 page= 0 errs= 1 REAL TIME CLOCK - This active-low bit indicates that a real time clock interrupt is pending. It should power-up in the high state. Error message: stat= 2 adr= 7X4158 exp= 1 act= 0 page= 0 errs= 1 FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 6 REFRESH DISABLE - This active-high bit indicates that the DRAM refresh circuitry is disabled. It should power-up in the low or enabled state. Error message: stat= 3 adr= 7X4148 exp= 0 act= 1 page= 0 errs= 1 umentation Page 5 _ 3. _ _ 1. _ 1: _ This test verifies the basic integrity of both the CLB and IOP address, data, and control lines. The test consists of three parts: o All Command/Status bits that are affected by the power/up CLB reset sequence are tested for their correct values. o The Prom is then checksummed using CLB accesses via 'C' code. o The driving program then executes the selftest code which consists of the following sections: o The Prom is checksummed. o A shared memory confidence test is run. o The 'IOP' is tested for basic instruction execution capability. Upon power-up various status bits ar I/O PORTS ENABLE - This active-high bit indicates that the I/O ports are enabled. Its power-on state is I/O Ports Disbled or low. Error message: stat= 4 adr= 7X4148 exp= 0 act= 1 page= 0 errs= 1 FORCE BAD PARITY - This active-high bit forces any data written to memory to have bad parity. Its power-on state is disabled or low. Error message: stat= 5 adr= 7X4154 exp= 0 act= 1 page= 0 errs= 1 HANDSHAKE LOGIC ENABLE - This active-high bit enables the interrupt handshake circuitry. It should power-up in the diasabled or low state. Error message: stat= 6 adr= 7X415c exp= 0 act= 1 page= 0 errs= 1 IOP RESET - This active-low bit indicates that the IOP is being held in reset. It should power-up in the active-low state, IOP held in reset. Error message: stat= 7 adr= 7X4140 exp= 0 act= 1 page= 0 errs= 1 IOP HALT - This active-low bit indicates that the IOP is being held in the halted state. It should power-up in i e guaranteed to be in known states. The first part of this test verifies these conditions. These status bits along with their expected power-up values and error message outputs in case of failure are as follows: NOTE: Every error message reported when using the diagnostic is qualified with the associated test number. For brevity this initial portion of the error message will not be used throughout this document. The following information relates to error messages: The X in the error address (adr) will range from a-e depending on the slot being tested. In general throughout the testing the status value returned (stat) is just a quick indication of how far the test proceeded before an error was incurred. The status codes will begin at 1 for each test. Command/Status values: Doing a word read of any command/status location will return that location's status in bit 15. Throughout this document t ts active-low state. Error message: stat= 8 adr= 7X4144 exp= 0 act= 1 page= 0 errs= 1 All 16 Handshake enable and status bits should power-up in the inactive or low state. These bits are listed below along with their associated error messages. CLEAR PIO ACKNOWLEDGE ENABLE Error message: stat= 9 adr= 7X4000 exp= 0 act= 1 page= 0 errs= 1 SET PIO ACKNOWLEDGE ENABLE Error message: stat= 10 adr= 7X4010 exp= 0 act= 1 page= 0 errs= 1 CLEAR CLB ATTENTION ENABLE Error message: stat= 11 adr= 7X4008 exp= 0 act= 1 page= 0 errs= 1 SET CLB ATTENTION ENABLE Error message: stat= 12 adr= 7X4018 exp= 0 act= 1 page= 0 errs= 1 CLEAR PIO ACKNOWLEDGE FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 7 Error message: stat= 13 adr= 7X4004 exp= 0 act= 1 page= 0 errs= 1 SET PIO ACKNOWLEDGE Error message: stat= 14 adr= 7X4014 exp= 0 ac pre- specified locations (one location each for slots a-e). Status information is written to one of these locations depending on the slot occupied. Upon successful completion of the self-test a '0' is written the the appropriate location. These address' are as follows: Slot 'a' -> address 'a44' Slot 'b' -> address 'a86' Slot 'c' -> address 'ac8' Slot 'd' -> address 'b0a' Slot 'e' -> address 'b4c' An error condition will return one of the following hex error values: ERROR CODE INDICATION 1 <>Checksum error 2 <>Memory error 3 <>Instruction Execution error 4 <>Parity error Note that the special case in which no proms are installed will not produce a checksum error in either part 2 or part 3. _ 2. _ 2: _ t= 1 page= 0 errs= 1 CLEAR CLB ATTENTION Error message: stat= 15 adr= 7X400c exp= 0 act= 1 page= 0 errs= 1 SET CLB ATTENTION Error message: stat= 16 adr= 7X401c exp= 0 act= 1 page= 0 errs= 1 CLEAR CLB ACKNOWLEDGE ENABLE Error message: stat= 17 adr= 7X4002 exp= 0 act= 1 page= 0 errs= 1 SET CLB ACKNOWLEDGE ENABLE Error message: stat= 18 adr= 7X4012 exp= 0 act= 1 page= 0 errs= 1 CLEAR CLB ACKNOWLEDGE Error message: stat= 19 adr= 7X400a exp= 0 act= 1 page= 0 errs= 1 SET CLB ACKNOWLEDGE Error message: stat= 20 adr= 7X401a exp= 0 act= 1 page= 0 errs= 1 CLEAR PIO ATTENTION Error message: stat= 21 adr= 7X4006 exp= 0 act= 1 page= 0 errs= 1 SET PIO ATTENTION Error message: stat= 22 adr= 7X4016 exp= 0 act= 1 page= 0 errs= 1 CLEAR PIO ATTENTION ENABLE Error message: stat= 23 adr= 7X400e exp= 0 act= 1 page= 0 errs= 1 SET PIO ATTENTION ENABLE Error message: stat= 24 adr= 7X401e exp= 0 act= 1 page= 0 errs= This test verifies the integrity of all PIO command/Status bits, the CLB-access-only interrupt vector register, and the parallel ports. The first part tests the ability of the various command/status bits to be set and cleared. The handshake bits are 'touch' sensitive in that the process of writing to a particular set or clear location performs the indicated operation. An error condition will return the particular bits' address and the expected and actual values returned. The various bits tested along with their address' are listed under test 1.1. The status values returned are from 1 through 24. The second part tests the CLB-only accessable interrupt vector register using both walking '1' and walking '0' patterns. The following error status is returned: stat= 25 adr= 7X4041 exp= ? act= ? page= 0 errs= 1 The expected and actual values retuned are byte-wide quantiti The second part of Test 1.1 checksums the on-board EPROM using CLB accesses using 'C' code. This allows a controlled means of determining whether the Driver/Self-test code has degraded. The following error message is returned in case of failure: stat= 25 adr= ? exp= 0 act= ? page= 0 errs= 1 The address given will be the address of the last prom location FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 8 summed. The actual value returned will reflect the erroneous summation value. The expected summation value is 0. The third part of Test 1.1 has the driving program vector directly to the prom-based selftest code which it then executes. The following error message is returned in case of failure: stat= 26 adr= ? exp= 0 act= ? page= 0 errs= 1 The error address is a long word pointer to one of five es and FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 9 reflect the pattern written and the actual value returned. The third part of test 1.2 tests the parallel ports in both byte and word fashion using walking '1' and walking '0' patterns. The first three tests are run on the byte-wide ports 'a', 'b', and 'c' while the last two tests are run on the word-wide ports 'ab' and 'bc'. Note that this portion of the test will not be executed unless the enable parallel port testing command was issued and the special test fixture is not to be used. The default condition is parallel port testing disabled. The error information returned is as follows: Byte-wide Port 'a': stat= 26 adr= 7X6041 exp= ? act= ? page= 0 errs= 1 Byte-wide Port 'b': stat= 27 adr= 7X6010 exp= ? act= ? page= 0 errs= 1 The 8-bit window register then provides for 256 32K byte pages. Test 1.2 uses fixed mode access'. This test is identical to test 1.2 with the difference being that each CLB write cycle is done using a fixed mode access and each read access is done using a movable window access. Since the PIO I/O address space is located at the top of the memory map the window register is written with a value of 'fc' hex. The error information provided is identical with that returned from test 1.2 except that since all reads are done using the movable window bit 15 will always be high in the error address reported. For example if an error occured on a read from parallel port 'A' the error address would be given as 7X6041 in test 1.2 but if it occurred during this test it would be given as 7Xe041. Again note that the parallel port portion of the test will not be executed unless the enable parallel port testing command was issued. Byte-wide Port 'c': stat= 28 adr= 7X6101 exp= ? act= ? page= 0 errs= 1 Word-wide Port 'ab': stat= 29 adr= 7X6050 exp= ? act= ? page= 0 errs= 1 Word-wide Port 'bc': stat= 30 adr= 7X6110 exp= ? act= ? page= 0 errs= 1 The expected and actual values retuned are byte quantities for status 26 through 28 and word values for status 29 and 30. If the enable parallel port testing command was executed and the special test fixture is to be used three sets of byte-wide port loopback tests will be executed. These tests use the same patterns as for the previously described tests but write the patterns first to one port then test for the correct values to be read from the other two. This procedure is repeated for all three cases. The error information returned is as follows: Byte-wide Port 'a' loopback test: stat= 31 adr= 7X6010 exp= ? act= ? page= 0 errs= 1 stat= 32 adr= 7X6101 exp= _ 4. _ 4: _ This test verifies the 128K bytes (64K words) of shared memory with the DRAM refresh circuitry diasabled. All dynamic ram chips are tested for their ability to not fade with refresh withheld for a 2ms period. The PIO board multiplexes address lines a9-a16 for a hardware RAS-only refresh. This test turns off this hardware refresh and relies on a precisely controlled software refresh for testing purposes. A total of 256 RAS cycles (each refreshing a 256 word block) are needed within a 2ms period to refresh the entire memory. This test writes each 'block' with the word value '5555' and immediately after the last write (which refreshed the entire block) a precise 2ms timing period is entered. Part of this period is used to write the next block. After 2ms the first location is tested for fading (t ? act= ? page= 0 errs= 1 Byte-wide Port 'b' loopback test: stat= 33 adr= 7X6041 exp= ? act= ? page= 0 errs= 1 stat= 34 adr= 7X6101 exp= ? act= ? page= 0 errs= 1 Byte-wide Port 'c' loopback test: FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 10 stat= 35 adr= 7X6041 exp= ? act= ? page= 0 errs= 1 stat= 36 adr= 7X6010 exp= ? act= ? page= 0 errs= 1 _ 3. _ 3: _ d, _ The PIO card uses a CLB-write-only window register to allow CLB access to the full 8 Mbyte address space on the board. CLB address bit 15 provides the switch from the fixed mode of access (32K bytes) to the movable-window mode of access. Bit 15 high places the 8 window bits onto pio address lines 15-22 (address line 23 is not used). his read refreshes the entire block), followed by the rest of the block in succession. This algorithm is repeated in succession for all 256 blocks covering four pages of 16K words each. Upon successful completion of this entire pass the test is repeated using the inverted pattern 'aaaa'. In case of failure the following error information is returned: stat= 1 adr= ? exp= ? act= ? page= ? errs= 1 The expected pattern will be the word value '5555' or 'aaaa' as applicable. The failed address will range from 7X8000 through 7Xffff with the page number value from 0 through 3 indicating which 16K word page was being addressed when the failure occurred. A status value of 2 returned indicates that a parity error occurred FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 11 sometime during the test but that the test was ot pt that is occurring. Error information ordered by status number is as follows: stat= 1 adr= 7X4150 exp= 0 act= 1 page= 0 errs= 1 A status value of '1' indicates that after forcing a parity error to occur on the high byte only the reading of the Parity Error status bit did not return the expected active low value. stat= 2 adr= 7X4150 exp= 1 act= 0 page= 0 errs= 1 A status value of '2' indicates that the parity error occurred as expected but that after disabling the Force Bad Parity Enable bit, writing the same byte test location with good parity and reading it again the Parity Error Status bit was still active. FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 12 stat= 3 adr= 7X4150 exp= 0 act= 1 page= 0 errs= 1 A status value of '3' indicates that after forcing a parity error to occur on the low-byte only th herwise successfully completed. No specific information regarding the location, etc. is returned. Upon successful completion of this test the refresh circuitry is enabled. _ 5. _ 5: _ The purpose of this test is to separately verify the high and low byte parity generation and check logic. The ram parity logic writes a parity bit with each byte written to the dual-port ram. When read, this parity bit is checked and if a parity error occurs, indicating either a hard or soft error, two actions take place: o A non-maskable level 7 interrupt is sent to the IOP o The Parity Error status bit is set To facilitate the testing of this logic there exists the ability, via a software controlled bit, to write bad parity to memory which in turn when read will force a parity error to occur. For this low-level test the IOP is e reading of the Parity Error status bit did not return the expected active low value. stat= 4 adr= 7X4150 exp= 1 act= 0 page= 0 errs= 1 A status value of '4' indicates that the parity error occurred as expected but that after disabling the Force Bad Parity Enable bit, writing the same byte test location with good parity and reading it again the Parity Error Status bit was still active. _ 6. _ 6: _ This test verifies that the IOP can be started and that it can read from memory. It also indicates that the local data bus is in good shape and that the data lines are not transposed from the CLB data lines. The first operation consists of memory initialization. This initialization consists of the following operations: o A long word write of the hex value 4e704e72 (reset/stop instruction sequence) to all of memo held in reset so that only the ability of the host 68000 to force a parity error and cause the setting of the Parity error flag will be tested. With the IOP continuing to be held in reset the Force Bad Parity bit is asserted and a high-byte write cycle is executed. An arbitrary value is written to ram since a force bad parity condition is data independant. The same location is then read and the Parity Error bit tested for assertion. The Force Bad Parity and Parity Error bits are then reset by first writing a '0' to Force Bad Parity and Enable Parity Error, then writing a '1' to Enable Parity Error. The same location is again written and read to verify that no parity error is generated. This sequence is then repeated to test the low-byte parity generation and check logic. Note that since both the reset and halt lines are being asserted the IOP is not able to field the level seven interru o Long locations 0, 4, 400, and 404 (hex) are written with the values 1fffe, 400, 42780600, and 4e722700 (hex) respectively. The test continues with the IOP reset and halt lines being released. The IOP should then load the System Stack pointer with the long word value from location 0 (1fffe hex) and load the Program Counter with the long word value from location 4. Since long location 4 contains the hex value 400 the IOP will begin instruction execution there. Vectoring to location 400 the IOP should execute the instruction sequence 'clrw 0x600; stop #0x2700'. The host processor has previously written the value '0' to the Bus Window Address register (indicating page '0' accesses through the movable window) and polls location 600 hex for its cleared state. When this occurs the host then tests the halt and reset status bits for their correct (inactive) states. The following error stat ul comparison the same location is written with the left shifted pattern (0002 hex). This method repeats until the '1' has been walked across the entire test pattern word. The walking '0' test is conducted in byte fashion with the byte pattern 'fe' hex written to all byte locations in memory. Each location is then read, compared with the expected pattern 'fe' and written with the new pattern 'fd'. The test proceeds until the '0' has been walked entirely across the test pattern. Upon successful completion of this test the memory is written with values specifically for test 1.8. This initialization consists of the following operations: o Write the instruction sequence 'reset; stop #0x2700' to location'400' hex. o Fill the rest of memory with a 'reset; stop' instruction sequence ('4e704e72' hex). Note that if an error occurs this final operation will n values are possible: stat= 1 adr= 7X8600 exp= 0 act= ? page= 0 errs= 1 Error status 1 indicates that the host processor timed out while waiting for the IOP to execute the clrw 0x600 instruction. Note that as a result of the initialization process location 600 was written with the hex value 4e72. stat= 2 adr= 7X4144 exp= 1 act= 0 page= 0 errs= 1 Error status 2 indicates that the clrw 0x600 instruction was correctly executed by the IOP but that the IOP is in the halted FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 13 state (possibly caused by a double bus error). stat= 3 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Error status 3 indicates that the clrw 0x600 instruction was correctly executed by the IOP but that the IOP reset line is active. stat= 4 adr= 7X4140 exp= 1 act= 0 page= 0 errs= happen thereby causing the subsequent failure of Test 1.8. The Test 1.8 failure will in turn cause Test 1.9 to fail. For this reason Tests 1.8 and 1.9 will not be run if a Test 1.7 error is incurred. The normal pass messages will not be printed. The error information FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 14 returned is as follows: stat= 1 adr= ? exp= ? act= ? page= ? errs= 1 The expected pattern and actual value read will be byte or word values as applicable. The failed address will range from 7X8000 through 7Xffff with the page number value from 0 through 3 indicating which 32K byte page is being addressed. A status value of 2 returned indicates that a parity error occurred sometime during the test but that the test was otherwise successfully completed. No specific information regarding the Error status 4 indicates that both the halt and reset lines are in their active-low states. Note that since both Tests 1.8 and 1.9 are dependent upon the successful completion of Test 1.6 (by its placing the IOP in a stopped state) these two tests will not be run if a Test 1.6 error is incurred. The normal pass messages will not be printed. _ 7. _ 7: _ The purpose of this test is to verify that shared memory funtionality is not affected by the enabling of the refresh logic. The test commences with the enabling of the refresh circuitry. Walking '1', walking '0' test patterns are then used in the following manner: First the 16-bit hex pattern 0001 is written to all word locations in memory. Next each location is read, compared with the expected pattern (0001 hex), and after a successf location, etc. is returned. _ 8. _ 8: _ This test is a repeat of Test 1.5 but since the IOP is now in a stopped state as a result of the correct execution of test 1.6 a forced parity error as described earlier will cause a non-maskable level 7 interrupt to the IOP. As a consequence of test 1.4's IOP startup sequence and execution of the 'stop #0x2700' instruction at hex location 400 the IOP will only respond to a level seven interrupt. The Force Bad Parity bit is set to generate bad parity. An arbitrary word value is then written to memory and the same location read to cause a parity error. This will cause a level seven interrupt to occur with IOP processing as follows: o A temporary copy of the status register is made, and the status register is set for exception processing. ndicates that the expected stacked program counter (low-order word) value of 408 hex was not read. stat= 4 adr= 7Xfffa exp= 0 act= ? page= 3 errs= 1 A status value of '4' indicates that the expected stacked program counter (high-order word) value of 0 was not read. stat= 5 adr= 7Xfff8 exp= 2700 act= ? page= 3 errs= 1 A status value of '5' indicates that the expected stacked status register (high-order word) value of 2700 hex was not read. stat= 6 adr= 7X4144 exp= 1 act= 0 page= 0 errs= 1 Error status 6 indicates that the stacked values were correctly found by the host processor but that the IOP is in the halted state (possibly caused by a double bus error). stat= 7 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Error status 7 indicates that the stacked values were correctly found by the host processor but that the IOP is in the reset state. stat= 8 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Error status 8 indica o The IOP then reads the lower byte from PROM word location 7ffffe. Since a prom is not installed the value read is indeterminate and could therefore range from 0 to ff. This byte is then internally multipled by four to provide a possible 256 long word vector locations. To allow for any prom value to be read memory locations 0 through 3fc have been previously written with the hex address o The IOP stacks the current program counter value (408 hex) and its saved copy of the status register (2700 hex) using the supervisor stack pointer which was set to 1fffe hex previously (test 1.6). o The processor then vectors to memory location '400' which con- tains the instruction sequence 'reset; stop #0x2700' which is then executed. The test proceeds with the host processor testing for correct parity error generation as was done in test tes that both the halt and reset lines are in their active low states. Note that if an error occurrs Test 1.9 will also fail. For this reason Test 1.9 will not be run if a Test 1.8 error is incurred. The normal pass message will not be printed. _ 9. _ 9: _ This test verifies the functionality of the PIO refresh logic. After a long (~3s) delay the memory is again searched for the stacked program counter low and high words and the status register value. Error information ordered by status number is as follows: FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 16 stat= 1 adr= 7Xfffc exp= 408 act= ? page= 3 errs= 1 A status value of '1' indicates that the expected stacked program counter (low-order word) value of 408 hex was not read. stat= 2 1.5 and then testing memory beginning at location 1fffc for the correctly stacked program counter and status register values. Error information ordered by status number is as follows: FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 15 stat= 1 adr= 7X4150 exp= 0 act= 1 page= 0 errs= 1 A status value of '1' indicates that after forcing a parity error the reading of the Parity Error status bit did not return the expected active low value. stat= 2 adr= 7X4150 exp= 1 act= 0 page= 0 errs= 1 A status value of '2' indicates that the parity error occurred as expected but that after disabling the Force Bad Parity Enable bit, writing the same byte test location with good parity and reading it again the Parity Error Status bit was still active. stat= 3 adr= 7Xfffc exp= 408 act= ? page= 3 errs= 1 A status value of '3' i adr= 7Xfffa exp= 0 act= ? page= 3 errs= 1 A status value of '2' indicates that the expected stacked program counter (high-order word) value of 0 was not read. stat= 3 adr= 7Xfff8 exp= 2700 act= ? page= 3 errs= 1 A status value of '3' indicates that the expected stacked status register (high-order word) value of 2700 hex was not read. FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 17 _ 4. _ The IOP-based tests are executed with the host 68000 as overseer. With the IOP held in a full reset state (both halt and reset lines asserted) executable code is written to the dual-port memory. The software controlled reset and halt lines are then deasserted. IOP test execution then commences with the host processor in a test-dependent ti ped state. The host processor had previously cleared this address. In this fashion address lines A17-A22 are minimally tested. As soon as the IOP is released to begin test execution the host processor enters a constant timing loop to allow sufficient lime for the completion of the IOP processing. If an error occurrs one of the following status values along with its related information is returned: stat= 1 adr= 7X4144 exp= 1 act= 0 page= 0 errs= 1 Error status 1 indicates that The IOP is halted abnormally (probably due to a double bus error while running amuck). The processor should have entered the stopped state (with halt and reset lines inactive or 'high') in a controlled fashion regardless of 'normal' error occurences defined below. stat= 2 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentati ming loop awaiting an IOP generated response. This response is generally a controlled alteration of a CLB-preset memory location. Note that in this series of tests (IOP hosted) each will run independently of the others. No test relies upon another for its proper execution. _ 1. _ 1: _ This lowest level IOP-based test determines if any address line interaction exists between IOP address lines beginning with address line A7 and through A16. Address lines A17-A22 are minimally tested along with the IOP data bus. Based on the success of previous testing, IOP address lines A1-A6 along with the upper and lower data strobes are assumed valid. An executable program of under 64 words is downloaded to the shared memory and the reset/halt lines deasserted. This test program uses a probe method on the 128K bytes of shared memory to verify the on Page 18 Error status 2 indicates that the IOP is reset (active low) abnormally. stat= 3 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Error status 3 indicates that both the halt and reset lines are in their active-low states. stat= 4 adr= 7X4150 exp= 1 act= 0 page= 0 errs= 1 Error status 4 indicates that a parity error occurred sometime during IOP test execution. stat= 5 adr= ? exp= 0 act= ? page= 0 errs= 1 Error status 5 indicates that an address line interaction problem exists. The particular address line causing the problem will be indicated by the error address returned which will range from '80' to '10000' as indicated above. The expected value of '0' comes from the memory address '0' value that was initially written. The actual value read should indicate the test pattern ('55' or 'aa') used. stat= 6 adr= ? exp= ffff act= ? page= 0 errs= 1 Error status 6 indicates that lack of address line interaction. The algorithm begins by using the memory address associated with the lowest unverified address line. In this case since the program to be downloaded is over 64 bytes but under 128 bytes address line A7 is the first line to be tested. Address line A7 'low' implies testing memory location '7e' and A7 'high' implies location '80'. Test pattern value '55' is written to each of these locations in turn and memory locations '3e' and '0' (which were previously written with values 'ffff'and '0' respectively) tested for any interaction. This process continues with locations 'fe' and '100' next being written and locations '3e' and '0' again tested for interaction. The final locations tested (for address line A16) are 'fffe' and '10000'. The entire test is then repeated using the test pattern 'aa'. The final operation has the IOP writing a value to Pio port address 7e6050 before entering its stop an address line interaction problem exists. The particular address line causing the problem will be indicated by the error address returned which will range from '7e' to 'fffe' as indicated above. The expected value of 'ffff' comes from the memory address '3e' value that was initially written. The actual value read should indicate the test pattern ('55' or 'aa') used. stat= 7 adr= 7X6150 exp= aaaa act= ? page= 0 errs= 1 Error status 7 indicates that a problem exists either with address lines A17-A22 or with the data lines. The basic funtionality of Port 'AB' (address 7X6150) was tested from the CLB side previously (Test 1.2 and 1.3). Since this port was cleared initially from the CLB side, if the actual value read was '0' it indicates that the addressing could be the problem. If the value read is close to 'aaaa' it indicates that a data line problem probably exists. _ 2. _ 2: _ urs it indicates that during the host processor's scanning of the IOP memory test space none of the possible test patterns was found. Possible patterns left from previous testing are also taken into account. stat= 2 adr= 7X4144 exp= 1 act= 0 page= 0 errs= 1 Error status 2 indicates that The IOP is halted abnormally (probably due to a double bus error while running amuck). The processor should have entered the stopped state (with halt and reset lines inactive or 'high') in a controlled fashion regardless of 'normal' error occurences defined below. stat= 3 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Error status 3 indicates that the IOP is reset (active low) abnormally. stat= 4 adr= 0 exp= 1 act= 0 page= 0 errs= 1 Error status 4 indicates that both the halt and reset lines are in their active-low states. stat= 5 adr= 7X4150 exp= 1 act= 0 page= 0 errs= 1 Error status 5 indica This test verifies that the shared memory arbitration circuitry functions correctly with both the host and IOP processors simultaneously making memory access'. The test begins with the host 68000 down-loading the IOP executable program. The halt and reset lines are then deasserted with the IOP commencing program execution. The stack pointer is set to the top of memory (address '1fffe'). The IOP will execute the same rotating '1' then '0' pattern memory tests used in Tests 1.4 and 1.6. While the IOP test is executing the host processor will alternately test a small section of memory (word locations 7X8200 through 7X820e), in order FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 19 to drive the data lines, then scan the memory space being tested by tes that a parity error occurred sometime during IOP test execution. stat= 6 adr= ? exp= ? act= ? page= 0 errs= 1 Error status 6 indicates that upon finding an unacceptable scan pattern value memory location 1000 was then tested for a cleared state (indicating successful IOP test completion) but that it was not found. The host then assumes that the IOP testing incurred a FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 20 memory error and stored the necessary error information for host access. This is then the error information returned. The address returned will range from 210 through 1fffe so that the page number is irrelevant. Also returned are the test pattern written by the IOP and the actual value read. Note that if an error status code of 8 through 12 occurs it indicates that the host's watchdog the IOP (hex word locations 210 through 1fffe) for acceptable values. The timing is such that four of these host 68000 loops are executed before the IOP memory test completes and clears location 1000 (which was initially written by the host processor). This is the IOP indication to the host that it has completing testing. The successful execution of this test ensures that no Dual-Port ram contention problems exist. If an error occurrs one of the following status values along with its related information is returned: stat= 1 adr= ? exp= ? act= ? page= 0 errs= 1 Error status 1 indicates that a pattern miscompare error occurred while the host processor was testing the memory space from 7X8200 through 7X820e. The expected values will be either '5555' or 'aaaa' which are the only test patterns used for this portion of the test. Note that if an error status code of 2 through 6 occ timing loop terminated while waiting for the IOP test completion indication. stat= 7 adr= 7X4144 exp= 1 act= 0 page= 0 errs= 1 Error status 7 indicates that the IOP is halted abnormally (probably due to a double bus error while running amuck). The processor should have entered the stopped state (with halt and reset lines inactive or 'high') in a controlled manner. stat= 8 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Error status 8 indicates that the IOP is reset (active low) abnormally. stat= 9 adr= 0 exp= 1 act= 0 page= 0 errs= 1 Error status 9 indicates that both the halt and reset lines are in their active-low states. stat= 10 adr= 7X4150 exp= 1 act= 0 page= 0 errs= 1 Error status 10 indicates that a parity error occurred sometime during IOP test execution. stat= 11 adr= 7X9000 exp= 0 act= ? page= 0 errs= 1 Error status 11 indicates the contents of memory location 1000 aft exp= 1 act= 0 page= 0 errs= 1 Error status 1 indicates that The IOP is halted abnormally (probably due to a double bus error while running amuck). The processor should have entered the stopped state (with halt and reset lines inactive or 'high') in a controlled fashion regardless of 'normal' error occurences defined below. stat= 2 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Error status 2 indicates that the IOP is reset (active low) abnormally. stat= 3 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Error status 3 indicates that both the halt and reset lines are in their active-low states. stat= 4 adr= 7X4150 exp= 1 act= 0 page= 0 errs= 1 Error status 4 indicates that a parity error occurred sometime during IOP test execution. stat= 5 adr= 7Xa000 exp= 0 act= ? page= 0 errs= 1 Error status 5 indicates that exception processing occured during the test. The number of exceptions that occur er the time-out occurred. It is then an indication (however slight) of what patterns (if any) that reside in memory. stat= 12 adr= 0 exp= 0 act= 0 page= 0 errs= 1 Error status 12 indicates that a time-out occurred but that location 1000 does contain the indication of IOP test completion (cleared state) although at this point (time-out) it is propably useless information. _ 3. _ 3: _ The Parallel Port test consists of two separate groups of tests. Neither of these will be executed unless the enable parallel port testing command was executed. The default condition is parallel port testing disabled. In the default case no testing will occur and no messages related to this test will be printed. For the case that no special test fixture (loopback device) is to be used the test has the IOP executing that code necessary to red is given by the actual value returned. Keeping track of these exceptions is accomplished by the IOP first loading the entire vector table with 256 long words of hex value (address) 400. Note that the vector table address range from 0 through 3fc and that the IOP executable code is down-loaded beginning at location 410. An interrupt handler is written to location 400 which increments location 2000 then returns. This location was initially cleared by the host processor. The returned address then is the CLB representation of PIO memory location 2000. Note that this method does not qualify which type(s) of exception occurred but that it does provide a useful indication for troubleshooting purposes. stat= 6 adr= ? exp= ? act= ? page= 0 errs= 1 FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 22 Error st FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 21 verify the read/write functionality of the various ports. Walking bit crosstalk patterns are first used to test the byte-wide paralell ports consists of the following operations: For the walking bit 'set' crosstalk pattern one bit is set in a field of 0's and written to all bytes/words (as appropriate). On the following seven/fifteen passes, the old byte/word pattern is verified before the next shifted bit pattern is written. For the walking bit 'reset' crosstalk pattern one bit is cleared in a field of 1's and written to all bytes/words (as appropriate). On the following seven/fifteen passes, the old byte/word pattern is verified before the next shifted bit pattern is written. Possible error information returned is as follows: stat= 1 adr= 7X4144 atus 6 indicates that a pattern miscompare error occured when a port value read was compared with that previously written. The returned address possible along with the associated port representation are as follows: Port 'B' address 7Xe010 Port 'A' address 7Xe041 Port 'AB' address 7Xe050 Port 'C' address 7Xe101 Port 'BC' address 7Xe110 The expected value returned will indicate both the size (byte or word) and the specific walking bit pattern used. If the enable parallel port testing command was executed and the special test fixture is to be used three sets of byte-wide port loopback tests will be executed. These tests use the same patterns as for the previously described tests but write the patterns first to one port then test for the correct values to be read from the other two. This procedure is repeated for all three ca reads the lower byte from prom word location 7ffffc (level 6 interrupt) to access a vector number. Since a prom could or could not be installed the value read is indeterminate and could therefor range from 0 to ff. This byte is then internally multipled by four to provide a possible 256 long word vector locations. This then allows for any prom value to be read. The interrupt handler is then written to location 400. It consists of the following operations: o Clear the interrupt o Reenable the interrupt o Increment location 1000 o Execute a return from exception instruction Note that location 1000 was initially cleared by the host. The IOP then enables the RTC interrupt and enters a short timing loop to allow an exact number of interrupts to occur before the loop terminates. This exact number is then recorded in location 1000 for use by the host. The IOP ses. Error status 6 will be indicated if a failure occurs as previously described. _ 4. _ 4: _ This test verifies the functionality of the Real-Time Clock circuitry. The Real-Time clock is a byproduct of the local dram refresh circuitry and provides a level 6 interrupt to the IOP every 1.875 ms when enabled. Its testing is accomplished in two stages: Static testing and dynamic testing. The static testing occurs while the IOP is in its full reset state so that an actual interrupt does not occur. Only the hosts ability to exercise the enable line, read the occurance of an interrupt and then reset it is tested in this stage of testing. If an error occurs here the following information is returned: stat= 1 adr= 7X4158 exp= 1 act= 0 page= 0 errs= 1 Error status 1 indicates that a real-time clock in then disables any further interrupts from occurring. The host has been in its own timing loop at this time to allow the IOP sufficient time to complete its testing. If a failure occurrs the following status messages are possible: stat= 3 adr= 7X4144 exp= 1 act= 0 page= 0 errs= 1 Error status 3 indicates that The IOP is halted abnormally (probably due to a double bus error while running amuck). The processor should have entered the stopped state (with halt and reset lines inactive or 'high'). stat= 4 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Error status 4 indicates that the IOP is reset (active low) abnormally. stat= 5 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Error status 5 indicates that both the halt and reset lines are in their active-low states. stat= 6 adr= 7X4150 exp= 1 act= 0 page= 0 errs= 1 Error status 6 indicates that a parity error occurred sometime during IOP test ex terrupt is pending at the onset of testing (active 'low'). Upon power-up this bit is guaranteed to be inactive or 'high'. stat= 2 adr= 7X4158 exp= 0 act= 1 page= 0 errs= 1 Error status 2 indicates that after enabling the real-time clock interrupt to occur it was not seen after a sufficient amount of time. The dynamic testing commences with the host 68K down-loading the IOP executable program beginning at location 410. The halt and reset lines are then deasserted with the IOP commencing program execution. The IOP begins by writing the status register with the value 2500 in order to allow a level 6 interrupt (RTC) to occurr. It then fills the entire vector table (locations 0-3fc) with long FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 23 word 400. This is necessary because during exception processing the IOP ecution. stat= 7 adr= 7X9000 exp= 5a act= ? page= 0 errs= 1 Error status 7 indicates that the correct number of interrupts (5a hex) did not occur and that the RTC interrupt line is active. The IOP executed program should have disabled the interrupt before terminating. The actual value returned represents the value of location 1000 (7X9000) and as such indicates the actual number of FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 24 interrupts that occurred. stat= 8 adr= 7X9000 exp= 5a act= ? page= 0 errs= 1 Error status 8 indicates that the correct number of interrupts (5a hex) did not occur and that the RTC interrupt line is inactive as it should be. The actual value returned represents the value of location 1000 (7X9000) and as such indicates the actual number of interrupts that occurred. _ 5. _ xp= 0 act= dead page= 0 errs= 1 Error status 2 indicates that the host processor took an interrupt(s). The location 'ffe' was initially set to 0 and is FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 25 written with the value 'dead' each time any exception processing occurrs before executing a return from exception instruction. It is strickly a safety measure against system hanging. stat= 3 adr= 7X4144 exp= 1 act= 0 page= 0 errs= 1 Error status 3 indicates that The IOP is halted abnormally (probably due to a double bus error while running amuck). The processor should have entered the stopped state (with halt and reset lines inactive or 'high'). stat= 4 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Error status 4 indicates that the IOP is reset (active low) abnormally. stat= 5 adr= 7X4140 e 5: _ The purpose of this test is to verify that the IOP cannot inadvertantly alter CLB access-only bits and registers. The test consists of four parts: o Bus Window Address Register Protection o Interrupt Vector Register Protection o CLEAR PIO ACK ENABLE Protection CLEAR CLB ATN ENABLE Protection o SET PIO ACK ENABLE Protection SET CLB ATN ENABLE Protection CLR PIO ACK Protection CLR CLB ATN Protection Each of the four parts have the IOP (via down-loaded programs) trying to write to areas that are protected. Protected in this case meaning that only the host processor (via the CLB) can write to these areas. In order to provide a controlled means of test termination for those portions of the testing that could inadve xp= 1 act= 0 page= 0 errs= 1 Error status 5 indicates that both the halt and reset lines are in their active-low states. stat= 6 adr= 7X4150 exp= 1 act= 0 page= 0 errs= 1 Error status 6 indicates that a parity error occurred sometime during IOP test execution. stat= 7 adr= 7Xa000 exp= 0 act= ? page= 0 errs= 1 Error status 7 indicates that the IOP took a number of interrupts given by the actual value returned. This location (2000 hex) is initially set to 0 by the IOP and is incremented each time any exception processing occurrs. It is strickly an indication that some sort of IOP Exception processing occurred. For Part 2 the CLB writes the value '40' to the vector register. The host processor then enters a timing loop during which it polls its own memory location 1000 for the cleared state and Pio memory location 1000 for its cleared state. Both of these locations have been previousl rtantly 'hang' the host processor (CLB side), all of the host processor vector table area is set-up to vector to a common interrupt handler routine. If this inadvertantly happens the keyboard bell will ring along with an error message to the effect that this has happened. For Part 1 the CLB writes the value '5a5a' to memory location 7x8ff0 with the window register set to page 0. The host processor then enters a timing loop during which it reads the same location and tests for the correct value previously written. At the same time the IOP is trying to write the window register with other page values trying to force an error. If an error occurrs during part 1 the following error messages are possible: stat= 1 adr= 7X8ff0 exp= 5a5a act= ? page= 0 errs= 1 Error status 1 indicates that the IOP was able to alter the window register and cause the host processor to read from another page. stat= 2 adr= ffe e y written with some other value. The former condition is the indication that the correct exception processing occurred and the later is the indication that the IOP has terminated its processing. At the same time the IOP program being executed is trying to write the protected vector register with various values in a small loop before interrupting the host processor. If the IOP succeeded in altering the vector regiser value the host will vector to the incorrect error handler. If this happens the bell will sound along with a status value to this effect. Vectoring to the correct handler will clear location 1000 thereby terminating the loop. If an error occurrs during part 2 the following error messages are possible: stat= 8 adr= 7X4041 exp= 40 act= ? page= 0 errs= 1 Error status 8 is the indication that the IOP was able to alter the FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 e host processor initially disabling the two interrupts to itself. The code executing on the IOP then enters a loop during which it tries to enable both interrupts then in turn set both interrupts. The key point here it that the enables should be IOP write protected. At the same time the host processor is also in a loop during which it tests both enables to see if the IOP was able to enable them. If an error occurrs during part 3 the following error messages are possible: stat= 15 adr= 7X4018 exp= 0 act= 1 page= 0 errs= 1 FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 27 Error status 15 is the indication that the IOP was able to beat the protection and enable the CLB Attension interrupt to occur. stat= 16 adr= 7X4010 exp= 0 act= 1 page= 0 errs= 1 Error status 16 is the indication that the IOP was able to beat the prote PIO Test Implementation Documentation Page 26 vector register thereby causing the host processor to vector to the incorrect error handler. CLB memory location ffe will then have the value 'dead' written to it as in Part 1 above. The address returned is the vector address along with the value originally written and the value actually read. The values the IOP atempted to alter it with are '0', 'ff', '55', and 'aa'. stat= 9 adr= 7X4144 exp= 1 act= 0 page= 0 errs= 1 Error status 9 indicates that The IOP is halted abnormally (probably due to a double bus error while running amuck). The processor should have entered the stopped state (with halt and reset lines inactive or 'high'). stat= 10 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Error status 10 indicates that the IOP is reset (active low) abnormally. stat= 11 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Erro ction and enable the PIO Acknowledge interrupt to occur. stat= 17 adr= ffe exp= 0 act= dead page= 0 errs= 1 Error status 17 indicates that the host processor took an interrupt(s) other than the two actually possible from the PIO. The location 'ffe' was initially set to 0 and is written with the value 'dead' each time any 'abnormal' exception processing occurrs. A return from exception instruction is then executed. This handler is used as a safety measure against system hanging. Since a common 'abnormal' exception handler is used it is not known exactly what sort of excetion(s) occurred. stat= 18 adr= 7X4144 exp= 1 act= 0 page= 0 errs= 1 Error status 18 indicates that The IOP is halted abnormally (probably due to a double bus error while running amuck). The processor should have entered the stopped state (with halt and reset lines inactive or 'high'). stat= 19 adr= 7X4140 exp= 1 act= 0 page= 0 r status 11 indicates that both the halt and reset lines are in their active-low states. stat= 12 adr= 7X4150 exp= 1 act= 0 page= 0 errs= 1 Error status 12 indicates that a parity error occurred sometime during IOP test execution. stat= 13 adr= 7Xa000 exp= 0 act= ? page= 0 errs= 1 Error status 13 indicates that the IOP took a number of interrupts given by the actual value returned. This location (2000 hex) is initially set to 0 by the IOP and is incremented each time any exception processing occurrs. It is strickly an indication that some sort of IOP Exception processing occurred. stat= 14 adr= 1000 exp= 0 act= bad page= 0 errs= 1 Error status 14 indicates that the interrupt to the host processor by the IOP must not have occurred since location 1000 was not cleared. The value 'bad' was initially written and should have been cleared by as part of the interrupt handler routine. Part 3 has th errs= 1 Error status 19 indicates that the IOP is reset (active low) abnormally. stat= 20 adr= 0 exp= 1 act= 0 page= 0 errs= 1 Error status 20 indicates that both the halt and reset lines are in their active-low states. stat= 21 adr= 7X4150 exp= 1 act= 0 page= 0 errs= 1 Error status 21 indicates that a parity error occurred sometime during IOP test execution. stat= 22 adr= 7Xa000 exp= 0 act= ? page= 0 errs= 1 Error status 22 indicates that the IOP took a number of interrupts given by the actual value returned. This location (2000 hex) is initially set to 0 by the IOP and is incremented each time any exception processing occurrs. It is strickly an indication that some sort of IOP Exception processing occurred. stat= 23 adr= 1000 exp= 5a5a act= 0 page= 0 errs= 1 Error status 23 indicates that even though the IOP apparently wasn't able to enable the two host interrupts (no error status a safety measure against system hanging. Since a common 'abnormal' exception handler is used it is not known exactly what sort of excetion(s) occurred. stat= 27 adr= 7X4144 exp= 1 act= 0 page= 0 errs= 1 Error status 27 indicates that The IOP is halted abnormally (probably due to a double bus error while running amuck). The processor should have entered the stopped state (with halt and reset lines inactive or 'high'). stat= 28 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Error status 28 indicates that the IOP is reset (active low) abnormally. stat= 29 adr= 0 exp= 1 act= 0 page= 0 errs= 1 Error status 29 indicates that both the halt and reset lines are in their active-low states. FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 29 stat= 30 adr= 7X4150 exp= 1 act= 0 page= 0 errs= 1 Error status 30 indica or 16), exception processing for one or both interrupts (dedicated FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 28 handler) occured. The value '5a5a' was initially written to location 1000 and is cleared as part of this specific interrupt handler routine. Part 4 begins with the host processor enabling both interrupts to itself. The code executing on the IOP then enters a loop during which time it tries to disable both interrupt enables then in turn sets both interrupts and immediately tries to clear them. The key point here it that the enables (both setting and clearing) should be IOP write protected. Clearing the two enables is also protected. At the same time the host processor is also in a loop during which time it tests both enables to see if the IOP was able to disable them. Note that correct operation tes that a parity error occurred sometime during IOP test execution. stat= 31 adr= 1000 exp= 2e7 act= ? page= 0 errs= 1 Error status 31 indicates that the correct number of interrupts to the host processor (based on known good boards) did not occurr. Location 1000 is initially cleared and is incremented each time a PIO-based host exception occurrs. stat= 32 adr= 7Xa000 exp= 0 act= ? page= 0 errs= 1 Error status 32 indicates that the IOP took a number of interrupts given by the actual value returned. This location (2000 hex) is initially set to 0 by the IOP and is incremented each time any exception processing occurrs. It is strickly an indication that some sort of IOP Exception processing occurred. _ 6. _ 6: _ The purpose of this test is to verify that the interrupt handshake logic is fuctional. Thr should cause '2e7' interrupts to be processed by the host processor. If an error occurrs during part 4 the following error messages are possible: stat= 24 adr= 7X4008 exp= 1 act= 0 page= 0 errs= 1 Error status 24 is the indication that the IOP was able to beat the protection and disable the CLB Attension interrupt from occurring. stat= 25 adr= 7X4000 exp= 1 act= 0 page= 0 errs= 1 Error status 25 is the indication that the IOP was able to beat the protection and disable the PIO Acknowledge interrupt from occurring. stat= 26 adr= ffe exp= 0 act= dead page= 0 errs= 1 Error status 26 indicates that the host processor took an interrupt(s) other than the two actually possible from the PIO. The location 'ffe' was initially set to 0 and is written with the value 'dead' each time any 'abnormal' exception processing occurrs. A return from exception instruction is then executed. This handler is used as ee groups of sub-tests are executed: Group 1 o IOP sets Main CPU interrupt w/o enable. o IOP sets Main CPU acknowledge w/o enable. o Main CPU sets IOP interrupt w/o enable. o Main CPU sets IOP acknowledge w/o enable. Group 2 o Main CPU sets IOP interrupt with enable. o Main CPU sets IOP acknowledge with enable. Group 3 o IOP sets Main CPU interrupt with enable. o IOP sets Main CPU acknowledge with enable. The Group 1 tests are static and as such successfull test execution only indicates that the relevant status register logic is functional. In the event some of this logic malfunctions and an interrupt to the host processor inadvetantly occurrs a controlled means of test termination is provided. A routine was executed at the onset that initialized the host processor vector table area and wrote tw ook an interrupt(s) which could have been caused by the PIO disable circuitry not working. stat= 5 adr= 7X4016 exp= 1 act= 0 page= 0 errs= 1 Error status 5 indicates that the PIO Attension interrupt to the IOP did not occur. Note that the IOP is in a full reset state at this time so this interrupt request has no effect on the IOP. stat= 6 adr= ffe exp= 0 act= dead page= 0 errs= 1 Error status 6 indicates that the host processor incurred some sort of 'abnornal' exception. stat= 7 adr= 7X401a exp= 1 act= 0 page= 0 errs= 1 Error status 7 indicates that the CLB Acknowledge interrupt to the IOP did not occur. Note that the IOP is in a full reset state at this time so this interrupt request has no effect on the IOP. stat= 8 adr= ffe exp= 0 act= dead page= 0 errs= 1 Error status 8 indicates that the host processor incurred some sort of 'abnornal' exception. FORTUNE SYSTEMS CONFIDENTIAL o interrupt handlers, one for the case of a valid interrupt occurance (to be used later for the dynamic testing) and the other to be used in the event of any other exception processing. If an unwanted interrupt or exception inadvertantly happens the keyboard bell will ring and an error message to this effect will be reported. The location 'ffe' was initially set to 0 and is written with the value 'dead' each time any 'abnormal' exception processing FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 30 occurrs. A return from exception instruction is then executed. This handler is used as a safety measure against system hanging. If an error occurrs during the part 1 testing one the following error messages will be reported: stat= 1 adr= 7X401c exp= 1 act= 0 page= 0 errs= 1 Error status 1 indicates that the CLB Attension in November 14, 1983 PIO Test Implementation Documentation Page 31 The Group 2 and 3 tests differ from the testing above in that all four interrupts will now be enabled and as such the testing can now be considered dynamic. The Group 2 testing commences with the host 68K down-loading the IOP executable program beginning at location 410. The halt and reset lines are then deasserted with the IOP commencing program execution. The IOP begins by writing the status register with the value 2200 in order to allow a level 3 interrupt to occurr. It then fills the entire vector table (locations 0-3fc) with long word 402. This is necessary because during exception processing the IOP reads the lower byte from prom word location 7ffff6 (level 3 interrupt) to access a vector number. Since a prom is not installed the value read is indeterminate and could therefor range from 0 to ff. This terrupt to the host processor did not occur. stat= 2 adr= ffe exp= 0 act= dead page= 0 errs= 1 Error status 2 indicates that the host processor took an interrupt(s) which could have been caused by the PIO disable circuitry not working. Normally the vector register is written with the value '40' so that in the event of a valid interrupt the correct exeption handler is executed. For the static tests the arbitrary value '33' was written to the vector register so that the 'abnormal' exception handler would be executed. Since a common 'abnormal' exception handler is used it is not absolutely known if some other sort of exception did occur. stat= 3 adr= 7X4014 exp= 1 act= 0 page= 0 errs= 1 Error status 3 indicates that the PIO Acknowledge interrupt to the host processor did not occur. stat= 4 adr= ffe exp= 0 act= dead page= 0 errs= 1 Error status 4 indicates that the host processor t byte is then internally multipled by four to provide a possible 256 long word vector locations. This then allows for any prom value to be read. The interrupt handler is then written to location 402. It consists of the following operations: o Clear the interrupt o Clear location 400 o Execute a return from exception instruction The IOP then then begins execution of a dummy routine awaiting the interrupt. The host then sets the appropriate interrupt and enters a short timing loop during which it polls location 400 testing for its cleared state (the indication that the IOP successfully handled the interrupt). Location 400 was previously written with the value 'bad'. If an error occurrs during the Part 2 testing one the following error messages will be reported: stat= 9 adr= 7X4144 exp= 1 act= 0 page= 0 errs= 1 Error status 9 indicates that The IOP is processor with its attension interrupt and then with its acknowledge interrupt. The host's means to handle these interrupts has been previously described. Basicly the correct responce by the host, via its vectoring to the correct exception handler, has it clearing its own memory location 1000. If an error occurrs during the Part 3 testing one the following error messages will be reported: stat= 19 adr= ffe exp= 0 act= dead page= 0 errs= 1 Error status 19 indicates that the host processor took an interrupt(s) other than the two actually possible from the PIO. The location 'ffe' was initially set to 0 and is written with the value 'dead' each time any 'abnormal' exception processing occurrs. A return from exception instruction is then executed. This handler is used as a safety measure against system hanging. Since a common 'abnormal' exception handler is used it is not known exactly wha halted abnormally (probably due to a double bus error while running amuck). The processor should have entered the stopped state (with halt and reset lines inactive or 'high'). stat= 10 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Error status 10 indicates that the IOP is reset (active low) abnormally. stat= 11 adr= 0 exp= 1 act= 0 page= 0 errs= 1 Error status 11 indicates that both the halt and reset lines are in their active-low states. stat= 12 adr= 7X4150 exp= 1 act= 0 page= 0 errs= 1 Error status 12 indicates that a parity error occurred sometime during IOP test execution. stat= 13 adr= 7X8400 exp= 0 act= bad page= 0 errs= 1 FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 32 Error status 13 indicates that the IOP interrupt handler was not entered so that location 400 was not cleared. stat= 1 sort of excetion(s) occurred. stat= 20 adr= 7X4144 exp= 1 act= 0 page= 0 errs= 1 Error status 20 indicates that The IOP is halted abnormally FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 33 (probably due to a double bus error while running amuck). The processor should have entered the stopped state (with halt and reset lines inactive or 'high'). stat= 21 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Error status 21 indicates that the IOP is reset (active low) abnormally. stat= 22 adr= 0 exp= 1 act= 0 page= 0 errs= 1 Error status 22 indicates that both the halt and reset lines are in their active-low states. stat= 23 adr= 7X4150 exp= 1 act= 0 page= 0 errs= 1 Error status 23 indicates that a parity error occurred sometime during IOP test execution. stat= 24 adr= 1000 exp= 0 act= bad page= 0 4 adr= 7X4144 exp= 1 act= 0 page= 0 errs= 1 Error status 14 indicates that The IOP is halted abnormally (probably due to a double bus error while running amuck). The processor should have entered the stopped state (with halt and reset lines inactive or 'high'). stat= 15 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Error status 15 indicates that the IOP is reset (active low) abnormally. stat= 16 adr= 0 exp= 1 act= 0 page= 0 errs= 1 Error status 16 indicates that both the halt and reset lines are in their active-low states. stat= 17 adr= 7X4150 exp= 1 act= 0 page= 0 errs= 1 Error status 17 indicates that a parity error occurred sometime during IOP test execution. stat= 18 adr= 7X8400 exp= 0 act= bad page= 0 errs= 1 Error status 18 indicates that the IOP interrupt handler was not entered so that location 400 was not cleared. The Group 3 testing has the IOP first interrupting the h errs= 1 Error status 24 indicates that the interrupt to the host processor by the IOP must not have occurred since location 1000 was not cleared. The value 'bad' was initially written and should have been cleared by as part of the interrupt handler routine. stat= 25 adr= ffe exp= 0 act= dead page= 0 errs= 1 Error status 25 indicates that the host processor took an interrupt(s) other than the two actually possible from the PIO. The location 'ffe' was initially set to 0 and is written with the value 'dead' each time any 'abnormal' exception processing occurrs. A return from exception instruction is then executed. This handler is used as a safety measure against system hanging. Since a common 'abnormal' exception handler is used it is not known exactly what sort of excetion(s) occurred. stat= 26 adr= 7X4144 exp= 1 act= 0 page= 0 errs= 1 Error status 26 indicates that The IOP is halted abnormall ~COPYRIGHT 1982 FORTUNE SYSTEMS CORPORATION. DISCLOSURE TO OTHERS PROHIBITED. FOR TERMS OF USE REFER TO LICENSE AGREEMENT. N^NuNV g,$| fPBn gl/< (probably due to a double bus error while running amuck). The processor should have entered the stopped state (with halt and reset lines inactive or 'high'). stat= 27 adr= 7X4140 exp= 1 act= 0 page= 0 errs= 1 Error status 27 indicates that the IOP is reset (active low) abnormally. stat= 28 adr= 0 exp= 1 act= 0 page= 0 errs= 1 Error status 28 indicates that both the halt and reset lines are in their active-low states. FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 PIO Test Implementation Documentation Page 34 stat= 29 adr= 7X4150 exp= 1 act= 0 page= 0 errs= 1 Error status 29 indicates that a parity error occurred sometime during IOP test execution. stat= 30 adr= 1000 exp= 0 act= bad page= 0 errs= 1 Error status 30 indicates that the interrupt to the host processor by the IOP must not have occurred since location 1000 was not cleare g|/< g"nl gT/< (@/< g$/< d. The value 'bad' was initially written and should have been cleared by as part of the interrupt handler routine. FORTUNE SYSTEMS CONFIDENTIAL November 14, 1983 NuNV N^NuNV N^NuNV N^NuNV N^NuNV g@-n g@ . f> . N^NuNV g@-n N^NuNV g,.< NuNV f*J* f$J* N^NuNV <<*| g(&| g@ y N^NuNV [6/< [6gJ/< N^NuNV N^NuNV gL`(3 gLN^NuNV @-P g,Jn N^Nu g,&| g@(< N^Nu NsNV g,(| g"$| g"`, . gJ/< N^NuNV g,$< `J S g@ S g@ S g@R. g" y N^Nu <|*| g(&| g@ A `hJ9 g,/. N^NuNV g,(< g,/. g@ y N^NuNV `& . N^NuNV gL/< N^NuNV g,$< g@ y f2J+ f,J+ N^NuNV N^NuNV g"/. \v/< \v/< N^NuNV g8$| SB( Qf&` SB( (@By N^NuNV g8`, yG g" N^NuNV yG g" R . N^NuNV g$fVJ N^NuNV `& . `& . N^NuNV N^NuNV @N^Nu g0&< g"$| gL/< N^NuNV g,$< `hJ9 g,/. N^NuNV N^NuNV `X y g8B( N^NuNV `z 9 gJJy `:/< N^NuNV N^NuNV N^NuNV N^NuNV N^NuNV N^NuNV RJ( a4`F N^NuNV g,$< g@ y fRJ, fLJ, N^NuNV gX0. `T/. N^NuNV f0`6 N^NuNV fl-| ` n PJ( ^gT`X 2~{` N^NuN N^Nu NuNuNu Nu o N^NuNV H@`6 N^Nu HABA N^NuNV B@H@ B@H@` N^Nu@(#)diag_copyrt.s 1.4 @(#)diag_srt.s 1.3 @(#)Fortune Systems Diagnostic Release 3.0 (2.14) not ready equip chk seek end missing addr mark not writable `&Jn N^Nu x(H` x(HB. *g*B n"" Lgnn xgd` xg:S n&H`J/ l p0` x&H DN^NuN N^NuN N^Nu gTJn data overrun data error end of cylinder missing data addr mark bad cylinder scan not satisfied scan hit wrong cylinder data field error control mark two side track 0 ready write protected fault fd0 busy fd1 busy fd2 busy fd3 busy ctrlr busy execute mode interrupt pending fxact fvfoe motor ena index hd load ena hd load timer Fortune Systems Floppy Disk Diagnostic Version %s (%s) Blocksize is set to %d, operating in %s mode with drive %d selected polled interrupt Hit HELP for command help. Valid commands: help, info, exit, initialize, specify, recalibrate, format, environment, seek, seek cycle, read, read ram, read id, read cycle, write, write ram, write cycle scan cycle, drive sense, drive select, drive interrupt mode, interrupt enable, interrupt disable, All words entered may be reduced to the minimum number of letters required to remain nonambiguous with other words. Type info for more information. current environment: step ra fX/< f&J. vg8/< N^Nu gTJn `Z . f:fI can't write to the diskette -- it's write protected! track to start test at track to stop test at rewrite disk every ?? pass(es) -- 0 for no writes both sides side 0 or 1 cycle test interrupted -- terminate test continuing./n/r writing scanning Scan error pass %d side %d track %d sector %d: 0x%x recalibrating to try to sync disk Write error pass %d side %d track %d: pass %d cum errors: %D Write (%D tries), %D scan (%D tries) pass %d (%s) @(#)fdvers.c 2.7.1.1 2.7.1.1 10/29/82 15:23:14 @(#)fd_util.c 2.5 initializing: using polled mode enabling interrupts... recalibrating drive %d... done ABORT: motor not up to speed, disk not present, or disk upside-down command sequence hung - controller not responding waiting for result f e. Any command can then be given. 2) Hitting the `CANCEL/DEL' key on the keyboard in response to any question will cause control to return to the command level. 3) On commands that are selected to run continuously, including the cycle test, hitting the `CANCEL/DEL' key will cause the command to abort gracefully and return to the command level. 4) For general testing, all parameters may be left at their default. 5) Operation may be in either interrupt or polled modes. Use int commands to toggle status. Initially is in interrupt mode. 6) Any of the four drives may be selected for operation. Use the drive commands to choose which one. 7) If the floppy controller appears hung (nothing happening on screen, and no noises are coming from the drive), hitting ESC will abort the current operation with an appropriate error message. exit floppy diagnostics. Invalid command (internal error). chip status (0x%x): controller status (0x%x): current bloc rom controller - not responding hung waiting for expected interrupt, which did not occur hung waiting for controller interrupt in polled mode probable hardware failure: head load timer inactive unknown cause You will need to use `initialize' command to reset the controller. phantom floppy interrupt unexpected floppy interrupt seek error: seek end bit not set: side %d track seek error: wrong id on side %d track %d result bytes: 0x%x %d @(#)rdcycle.c 2.2.1.1 (no compares) disk read cycle test (no data compares performed): track to start test at track to stop test at both sides side 0 or 1 read test interrupted -- terminate test continuing. pass %d cum read errors: %D errors out of %D blocks read pass %d side %d trk %d sec %d: @(#)getcmd.c 1.2 k size is %d currently operating in %s mode polled interrupt current drive selected is %d %2x (%d) - hit return Cyclic seek check: number of tracks to test maximum number is %d use default test tracks Enter track numbers to test: test track %d: track number side 0 number of test cycles step rate time - units of 2 ms seek cycle test terminated. Use 1k byte block size @(#)fdformat.c 2.3 I can't format the diskette -- it's write protected! Format disk - is scratch disk in drive %d interleave factor formatting disk format error: track %d select 0x%x: format error: media track %d (side %d) probably bad formatting complete. @(#)fdread.c 2.3 read tests - hit DEL to return to command level: track to read side 1 sector to read read error: read complete @(#)fdwrite.c 2.3 I can't write to the diskette -- it's write protected! write tests - hit DEL to return to command level: track to write side 1 sector to write write error: menu help initialize information exit quit specify recalibrate seek format read write scan status environment interrupt drive block cycle data ctrl control enable disable select status change mode sense 1024 command? command `%s' not recognized. command `%s' is ambiguous. argument `%s' not recognized. argument `%s' is ambiguous. @(#)diag_printf.c 1.5 (bootprt) (null) @(#)diag_param.c 2.5 %s (0x%X)? %s (%D)? that function key not recognized here. non-numerical entry. @(#)diag_yesno.c 2.4 %s (%s)? Please answer yes or no? @(#)diag_atoi.c 1.2 @(#)diag_gets.c 2.3 DEL @(#)diag_csavret.s 1.3 @(#)diag_setjmp.s 1.2 @(#)diag_initcrt.c 1.2 `*/< |$/< N^NuN N^NuN `4/< `d/< ~COPYRIGHT 1982 FORTUNE SYSTEMS CORPORATION. DISCLOSURE TO OTHERS PROHIBITED. FOR TERMS OF USE REFER TO LICENSE AGREEMENT. N^NuN *A-| rl n N^NuN N^NuN @/( A . zN^NuN N^NuN `4/. 8 @C N^NuN g$`&" jgh N^NuN N^NuN &A/< `*/< A"n A"n A"n A"n `*/< *H n N^NuN N^NuN @BP N^NuN (H`T g4 N^NuN *A . gj . gb-| mz . g2/< @/ N^NuN 9T=j gD n N^NuN kg^n jg8 . N^NuN (@ @J fF/, N^NuN A%P A%P A%P A%P A"m $A j ?gr2 @ h @ h N^NuN (H`\ N^NuN (H`T g4 N^NuN N^NuN q\/< `4/< N^NuN N^NuN N^NuN N^NuN N^NuN A*P>9 2 @ TfZB Tf0J q>Bj vP`N q> - N^NuN @JPm N^NuN A P-h &@ 9 $@-C rff&| $C 9 uf0/ N^NuN N^NuN N^NuN "DHn g"`J N^NuN "D&| N^NuN N^NuN N^NuN *A . gZ-| `J . @ . N^NuN f0 m dJSf BS/< N^Nu "D*C(DB `(D` N^NuN ,|$| cgBn jg|` N^Nu . @/ 2 @/ @/( N^NuN N^NuN `X/< N^NuN N^NuN N^NuN y Qg N^NuN N^NuN dg4/< g./< * @"n . @"n 2 @"n dg4/< f:/- 2 @-P dg0/< gJ/< A PN N^NuN N^NuN (H&| RtHn y Qg N^NuN N^NuN (H&| RtHn y Qg N^Nu *A(| @ h A-P A PN gJ/< g./< N^NuN A PN A P h A PN d`bp `^29 @ h N^NuN N^NuN *A-| `0/< * @/ A-P @ U h U h @ U h U h @ U h U h @ U h r$/< rH/< `*2. @!n @!C JPfF/< 4JPfJ/< ZJPfR/< U h `8 n f"-| op/< A PB q\/< U h @ U h U h @ U h N^NuN *AJ, g& . oB/< f\/9 U h U h ff-C U h @ U h gD . `4 . \`^p g./. @ h N^NuN *A2. $T l g" . g2/< `X . l2/< N^NuN N^NuN N^NuN N^NuN N^NuN N^NuN N^NuN RG0 SFJ@f N^NuN N^NuN *@-y N^Nu Nu"< NuJy NuNqNqNqNqNu/ _By Ns"< _By _By _By _By Ns 9 @j-n N^NuN Nm/9 N^Nu 5|& ? N^NuN N^NuN N^NuN N^NuN N^NuN (` 0 fBG` N^NuN N^NuN ESG0 RFSEf N^NuN x(H` x(HB. *g*B n"" N^NuN D~ ` Lgnn xgd` xg:S n&H`J/ l p0` x&H DN^NuN N^NuN N^NuN yG n N^NuN yG g N^NuN yG g N^NuN N^NuN N^Nu SLOT | DEVICE DRIVE TYPE CONTROLLER H # OF CYLS > # OF HEADS p BLKS/TRACK zBYTES/BLOCK INTERLEAVE R RWC CYL \WPRECMP CYL f ECC LENGTH READ WRITE FORMT SENSE INIT v LOOP COUNT 10304 SEQUENTIAL RANDOM DESTROY PROTECT READ TEST SEEK DMA TEST CMPWRT CMPRD WRT ERROR HARD ERR SOFT ERR DATA MISS PSOFT ERR DMA ERR NOT SAVED NOT RSTRD INCMPATBL TEST MODE START BLOCK END BLOCK TEST TYPE N^NuN N^NuN N^Nu NuNuNu "H". N^Nu < NuNV B@H@ B@H@` N^NuNV B@H@ H@`6 # OF HEADS R RWC CYL \WPRECMP CYL f ECC LENGTH READ r - read block WRITE w - write block NOP nop - No operation-invalid command seek SEEK seek - issue seek command recal RECAL recal - recalibrate drive FMTRK ft - format track RD L rdl - read long (w/ecc data) FMDSK fd - format disk WR L wrl - write long (w/ecc data) init INIT init - init drive characteristics @(#)xecmds.c 2.4 7 F8 F9 F10 F11 %s%c%c HOME CLR REP INV INC DEC CNT RAND EXIT PAGE WIN Byte = %3d Page = %d @(#)hist.c 2.7 %s%c%c READY FOR NEW COMMAND %s%c%cPAGE %c %s%c%c TErrors HErrors CErrors LErrors %s%c%c # address unit# loop count type %s%c%c %s%c%c EXECUTING COMMAND HISTORY .... %s%c%c %-7d %s%c%c %-7d %s%c%c %-7d %s%c%cPAGE %c %s%c%c %-7d %s%c%c %-9d %s%c%c %-7d %s%c%c READY FOR NEW COMMAND %s%c%c %-7d %s%c%c %s%c%c %s%c%c %-5d %s%c%c %s%c%c %-9d %s%c%c %s%c%c %-7d %s%c%c %-7d %s%c%c %-7d %s%c%c %-7d @(#)fd.c 2.2 @(#)seqtest.c 2.19 `%s%c%c %-3d %s%c%c %-3d %s%c%c %-3d %s%c%c %-3d %s%c%c %-5d %s%c%c SLOT: DMA: %s%c%c %-5d %s%c%c E D C B %s%c% UNIT NUMBER STEP RATE RETRIES ADDRESS BLOCK COUNT INTERLEAVE LOOP COUNT H # OF CYLS > # OF HEADS R RWC CYL \WPRECMP CYL f ECC LENGTH READ r - read block WRITE w _ write block sense SENSE sense - read sense bytes s - seek recal recal - recalibrate fd - format drive ctf - check track format ft - format track fbt - format bad track init INIT init - init drive characteristics tdr - test drive ready recc RDECC recc - read ecc burst length rd - ram diagnostics dd - drive diagnostics cid - internal ctlr diagnostics @(#)cmds.s 2.6 @(#)random.s 2.4 @(#)rand.c 1.1 %s%c%c* %s%c%c* %s%c%c* %s%c%c %-9d %s%c%c %-5d %s%c%c %-5d %s%c%c HIT ANY KEY ON KEYBOARD TO CONTINUE %s%c%c %-3d %s%c%c %-3d %s%c%c %-3d %s%c%c %-3d %s%c%c %s%c%c %s%c%c +%s: %c/%s/%x +%s: %s/%x %s%c%c %-5d %s%c%c %s%c%cWRITE %s%c%cREAD %s%c%c %-5d %s%c%c @(#)wdcmds.c 2.12 UNIT NUMBER STEP RATE RETRIES ADDRESS BLOCK COUNT INTERLEAVE BLK / TRACK LOOP COUNT @(#)version.c 3.1 10/3/83 20:54:17 @(#)crt.c 2.1 @(#)diag_printf.c 1.5 (null) @(#)diag_sio.c 1.3 @(#)diag_ctc.c 1.3 @(#)diag_csavret.s 1.3 @(#)diag_clrseg.s 1.2 SLOT = E DEVICE = RIGID DRIVE TYPE = A10 CONTROLLER = WD # OF CYLS = 153 # OF HEADS = 4 BLKS/TRACK = 17 BYTES/BLOCK = 512 INTERLEAVE = 2 WPRECMP CYL = 64 HELP F2 F3 F5 F6 F7 F8 F9 F16 > HELP FUNCTNS PARMS HIST DEV REP EDIT DIAGNOSTICS EXIT ***ERROR REPORT*** DISCRIPTION OF FUNCTION KEYS (hdtest initial screen) HELP - Displays the list of executable commands for the device currently selected. F1 - N/A F2 - FUNCTIONS SELECT (Functions Select Page 3) F3 - PARM DEFAULT SELECT (see Page 6) F4 - N/A F5 - COMMAND HISTORY (Command History Page 7) F6 - DEVICE (Device Select Page 9) F7 - REPEAT Re-execute last device command with the same parameters. F8 - EDIT (data buffer editor Page 10) F9 - DIAGNOSTICS (cyclic device tester Pa HARD DISK DIAGNOSTIC TEST IMPLEMENTATION DOCUMENTATION (RELEASE 1.1) Pat Harris Fortune Systems Corporation 101 Twin Dolphin Drive Redwood City, Ca. 94065 _ Diagnostic documentation on Hard Disk Diagnostics tests. Fortune Systems Internal Confidential. Distribution: Pat Patrick Trevor Fagerskog Peter Chen Darryl Phillips Dennis Moore Randy McDonald Lee Morse Pradip Morparia Wayne Painter November 14, 1983 F I D S - FAULT ISOLATION DIAGNOSTICS SYSTEM - VERSION 2 USER DOCUMENTATION AND INSTRUCTIONS Rev 1.1 ----------------------------------- TABLE OF CONTENTS ----------------- HDTEST MAIN ge 11) Special Keys: F10 - CANCEL/DEL - ABORT Return to command entry mode without executing command. F11 - EXECUTE - EXECUTE COMMAND Execute device command with parameters as specified. (LEFT cursor key) - Toggle message opposite prompt in the reverse direction. (RIGHT cursor key) - Toggle message opposite prompt in the forward direction. (UP cursor key) - Move to the previous promt. (DOWN cursor key) - Move to the next promt. FUNCTIONS SELECT Description - Positioned in the upper right-hand corner of the HDTEST main screen is a display depicting the cur- rent operating conditions and parameters. The functions select command allows the user to set the HDTEST options by querring each option and toggling through the parameters unique to that particular option. The 'DOWN cursor key' will step the cursor forward through the option list and the 'UP cursor key' will step in the reverse direction. Once positioned at a MENU DISPLAY .................... page 3 DISCRIPTION OF FUNCTION KEYS ................ page 4 a.) FUNCTIONS SELECT ................ page 5 b.) DEVICE .......................... page 7 PARMS DEFAULT SELECT MENU DISPLAY ........... page 8 a.) PARM DEFAULT SELECT ............. page 9 COMMAND HISTORY DISPLAY ..................... page 10 a.) COMMAND HISTORY ................. page 11 DATA BUFFER EDITOR DISPLAY .................. page 13 e.) DATA BUFFER EDITOR .............. page 14 DIAGNOSTICS TESTER MENU DISPLAY ............. page 15 f.) DIAGNOSTICS TESTER .............. page 16 HDTEST OPERATING SYSTEM OVERVIEW ............ page 17 PROCEEDURE OF OPERATIONS .................... page 18 Fortune Diagnostics Main Menu PARM TYPE = DEC DATA TYPE = HEX ERROR COUNT = ON DISP ERROR = ON DISP STATUS = ON ERROR TRAP = RUN ADDRESS = LOGIC HISTORY = OFF DISP UPDATE = ON given option, the 'RIGHT cursor key' will cause the allowable parameter to toggle forward. The 'LEFT cursor key' will toggle the available option list for a particular parameter backwards. 'F11', 'EXECUTE', 'CANCEL/DEL', or 'F10', will return the user back to command entry mode. Display - PARM TYPE = X DATA TYPE = X ERROR COUNT = X DISP ERROR = X DISP STATUS = X ERROR TRAP = X ADDRESS = X HISTORY = X DISP UPDATE = X PARM TYPE - Selects the numeric base in which the device command parameters are input and displayed. Also controls the base in which DMA errors, from the diagnostics tester (F9), display the logical disc address on the screen. Parm type parameters: HEX, DEC, OCT (hexidecimal, decimal, octal). DATA TYPE - same as above, but applies to the read/write data. Data type parameters: HEX, DEC, OCT (hexidecimal, decimal, octal). ERROR COUNT - Will turn the error counters either on or off. The 'on' mode allows active updating of cumula STORY - It is posible to enable or disable the command history recorder from functions select. For further infor- mation see COMMAND HISTORY. History parameters: OFF, ON, QUIET. DISP UPDATE - Turns ON or OFF the updating of the screen during history commands. Off provides a tighter loop during execution of a command history file. Loop parameters: OFF, ON. DEVICE Description - Display - SLOT = E DEVICE = RIGID DRIVE TYPE = A10 CONTROLLER = WD # OF CYLS = XX # OF HEADS = XX BLKS/TRACK = XX BYTES/BLOCK = XX INTERLEAVE = XX WPRECMP CYL = XX Allows the operator to select which type of device to test, under which controller, and which particular model, (if applicable). Currently HDTEST supports only a limited number of configurations, (see note at bottom). In the device environment list on the lower right side of the HDTEST main menu only the first three positions are "toggle" selectable and the others reflect the actual environmental details o tive error tallying, 'off' provides a more optimized code execution path by not having to update information on the display screen. Turning the error count option off then back on, in the command history, (F9), will reset the counters. In the diagnostics tester (F9) the counters are automatically reset. In the command history (F5) the error count display will show cumulative errors for all device commands executed since last reset, cumulative errors for the current device command executing, and cumulative errors occuring in any given loop of the current device command executing. Error count parameters: ON, OFF. DISP ERROR - At time of execution when an error occurs the reporting may take three forms, either none at all, just the device error bytes (displayed in hexidecimal), or both the device error bytes and a text error message. Disp error parameters: OFF, SENSE, ON. DISP STATUS - Display status will display a series of characters, representing the first character of the st f the device selected. ***NOTE: Version 2 is fixed for rigid disc testing only. Controller select is limited to the XEBEC and WD. Fortune Diagnostics Main Menu UNIT NUMBER = 0 PARM TYPE = DEC STEP RATE = 0 DATA TYPE = HEX ADDRESS = 0 ERROR COUNT = ON BLOCK COUNT = 1 DISP ERROR = ON INTERLEAVE = 2 DISP STATUS = ON BLK / TRACK = 17 ERROR TRAP = RUN LOOP COUNT = 1 ADDRESS = LOGIC # OF CYLS = 153 HISTORY = OFF # OF HEADS = 4 DISP UPDATE = ON WPRECMP CYL = 128 SLOT = E DEVICE = RIGID DRIVE TYPE = A10 CONTROLLER = WD # OF CYLS = 1 atus message, and dots, ".", representing their relative bit positions in the status word. Status will be displayed on the right hand side of the initial hdtest screen in between the functions display, and the device environment display. ERROR TRAP - While executing a command, or test, on the device under diagnosis any errors occuring may be trapped in one of four modes. Error trap parameters: RUN, STOP, LOOP, WAIT. The run parameter will continue processing and report the error as specified by the DISP ERROR option. Stop will halt processing of the command and report the error as specified by the DISP ERROR option. Loop will set processing in a tight endless loop, error reporting will occur only in the first pass through the endless loop. The wait parameter will report the error then wait for user acknowlegement, depressing any key on keyboard, before continuing processing. ADDRESS - Sets the device addressing mode to either logical or physical. Address parameters: LOGIC, PHYS. # OF HEADS = 4 BLKS/TRACK = 17 BYTES/BLOCK = 512 INTERLEAVE = 2 WPRECMP CYL = 64 HELP F2 F3 F5 F6 F7 F8 F9 > HELP FUNCTNS PARMS HIST DEV REP EDIT DIAGNOSTICS PARM DEFAULT SELECT For any given command to any particular device all of the default values for the command parameters are user selectable. By hitting carraige return in the first character position of any parameter the current default value will be displayed and subsequently used as data for that command parm. Display - UNIT NUMBER = XX STEP RATE = XX ADDRESS = XX BLOCK COUNT = XX INTERLEAVE = XX BLK / TRACK = XX LOOP COUNT = XX # OF CYLS = XX # OF HEADS = XX WPRECMP CYL = XX Command History TErrors HErrors CErrors LErrors 0 0 0 0 READY FOR NEW COMMAND # address unit# loop rmed on the command history file are: Delete, Append, Execute, Examine. Setting the command history mode switch to ON will cause a record of all commands executed in single entry mode to be stored. In the QUIET mode the commands are not executed, but just stored. This history file may be executed at any time. While executing, any errors encountered will be processed by the error trap handler, which can be set to RUN, STOP, WAIT, or LOOP on errors. Error reporting is governed by the DISP ERROR option. Any command that can be executed in single command entry format may be executed from a command history 'chain' file. - Description of Function Keys - ---------------------------- F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 EX DLH STO RCL DLC DLF MKD RET PAGE LST F1 - N/A F2 - EXECUTE HISTORY F3 - DELETE HISTORY FROM MEMORY F4 - STORE HISTORY FILE TO MINI-FLOPPY F5 - RECALL HISTORY FILE FROM MINI-FLOPPY F6 - DELETE LAST COMMAND IN HISTORY FILE FROM MEMORY F7 - DELET E HISTORY FILE FROM MINI-FLOPPY F8 - MAKE A DIRECTORY ON A FORMATED MINI-FLOPPY F9 - RETURN TO SINGLE COMMAND ENTRY MODE F10- DISPLAY NEXT PAGE OF COMMAND HISTORY F11- LIST DIRECTORY OF HISTORY FILES ON MINI-FLOPPY F2 EXECUTE HISTORY - Depressing F2 will cause the Command History, to prompt for a loop count, number of passes through the 'chain' file. After the loop count desired is entered, depressing F11 will cause execution, F10 will abort the execution of the command history prior to executing it. F3 LIST - Will erase the current command history file from memory. F4 STORE - Allows the user to 'build' command history files and save them on to mini-floppy with an assigned seven character name. No more than fifty files may be stored on any one mini-floppy. F5 RECALL - Recalls one user specified command history file from the mini-floppy and places it into memory, once in memory it can be executed(F11), appended to, commands deleted from it(F6), ...etc. F6 DELETE LAST - Cau count type 0 0 0 1 READ ***ERROR REPORT AREA*** 1 1000 0 1 WRITE ***ERROR REPORT AREA*** 2 2500 0 1 READ ***ERROR REPORT AREA*** 3 7500 0 1 WRITE ***ERROR REPORT AREA*** 4 5000 0 1 READ ***ERROR REPORT AREA*** 5 9000 0 1 WRITE ***ERROR REPORT AREA*** 6 8219 0 1 READ ***ERROR REPORT AREA*** 7 500 1 1 WRITE ***ERROR REPORT AREA*** 8 500 1 1000 READ ***ERROR REPORT AREA*** F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 EX DLH DLC RET PAGE LOOP = 1000 PAGE 1 COMMAND HISTORY Description - The command history allows a 'chain' of up to 100 device commands, with associated parameters, to be entered and stored in a tempory core file. The operations that may be perfo ses the removal of the last command in the command history file. It is useful if errors were made during the command entry process. F7 DELETE HISTORY M - Will delete one user specified command history file from the mini-floppy. F8 MAKE DIRECTORY - Initializes a mini-floppy for use by the command history for file storage and retrieval. F9 RETURN - Returns the operator back to the HDTEST device command entry mode. Data Buffer Editor Numeric data ascii data 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ........ number that can be randomly selected. END BLOCK - In sequential mode, this parameter is used as the ending block number with which to end the test, in random mode it is used as the largest logical block number that can be randomly selected. TEST TYPE - The Diagnostics Tester will perform a combination of selected command pattern tests on the device currently selected. There are five basic types of tests designed specificaly for the win- chester rigid discs. DESTROY: Writes the contents of the data buffer (see data buffer editor) out to a physical block on the disc, reads the block back into a separate test buffer, and then compares the two for data integrity. PROTECT: This test is the same as the DESTROY test except that the data block on the disc is first saved away and then restored after the block has been tested. Another read is then performed on the restored data but no compare is done on this second read. SEEK: Tests for any head ........ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 Row = 0 Col = 0 HOME CLR REP INV INC DEC CNT RAND EXIT PAGE WIN Byte = 0 Page = 1 DATA BUFFER EDITOR F1 - Move cursor to first location of buffer. F2 - Zero out the entire buffer. F3 - Replicate the first byte of the buffer throughout the entire buffer. F4 - Invert the contents of the entire buffer. F5 - Increment each byte in the buffer by one. F6 - Decrement each byte in t settling problems on the rigid disk. It first selects a random block in a cylinder one (1) increment away from its current position. It then reads that block and reseeks the original position, and then reseeks and writes the random block with its original data. After one full revolution, the block is reread to check for any errors. This process is repeated until the entire area of the disk has been scanned both forward and backwards. The cylinder increment is then changed to two (2) and the tests repeats. A loop is completed after a cylinder increment of 49 has been run on the disk. Note: this test is only valid in SEQUENTIAL mode. DMA TEST: Performs a DESTROY test command pattern on up to four controllers simultainously, this test was designed to analyze the bus conten- tion performance of the disc controllers in conjunction with the system. Only drive zero (0) on each of the controllers will be recognized during the DMA TEST. READ TEST: Used he buffer by one. F7 - Starting with the first byte, fill the buffer with an ascending order of data. F8 - Fill buffer with a random pattern of data. F9 - Return to HDTEST main menu. F10- Toggle display between the upper and lower 256 byte pages. F11- Toggle between numeric and ascii portions of display screen. Cyclic Device Test TEST MODE = SEQUENTIAL START BLOCK = 0 END BLOCK = 9197 TEST TYPE = PROTECT LOOP COUNT = 1 BLK HARD SOFT DATACMP WRTERRS 0 0 0 0 0 ** ERROR MESSAGES ** DIAGNOSTICS - Cyclic Device Tester TEST MODE - There are two modes of operation while executing test patterns. They are SEQUENTIAL, start from block START BLOCK and proceed sequentially to the end of the disc, RANDOM, randomly select the next block number. START BLOCK - In sequential mode this parameter is used as the block with which to start, in random it is used as the smallest logical bl to isolate bad blocks or hard errors rapidly. Only reads blocks no data compar- ison or integrity analysis is performed. CMPWRT: The compatibility test has two parts with a common function. This test and the CMPRD are used together along with two different systems. On the first system the CMPWRT portion of the test writes out a preset pattern to the entire disc. The data buffer is not used. The disc is then removed from the current system and physically transport- ed to any other system. CMPRD: After the CMPWRT has been performed and the disc has been moved to another system then CMPRD will read the entire disc and perform data integrity checks to identify system incompitabilities problems that might arise. LOOP COUNT - In sequential mode the loop count is used to count the number of times to execute test with previous parms reset before each pass. In random mode it signals the number of blocks to randomly select. Display - TEST MODE = SEQUEN hes to review the error information at time of occurance. Note: When entering commands with the command history in the 'quiet' or 'on' mode the write data select will not recognize 'ascii' input. If 'data type' is set to 'ascii', command history will force 'data type' into 'hex' mode. 3.) Test mode allows a preprogrammed test to exercise the device and detect faults or soft errors. HDTEST OPERATING SYSTEM - PROCEEDURE OF OPERATIONS MAIN MENU --------- On power up - restart the cursor will be positioned at the first entry of the device select window in the lower right hand corner of the main menu. It is at this time the appropriate device environment should be selected corresponding to the hardware present. If devices not physicaly attached to the system are selected HDTEST will hang and have to be restarted. Device select window - SLOT = E DEVICE = RIGID DRIVE TYPE = OTHER CONTROLLER = WD # OF CYLS = XXX # OF HEADS TIAL START BLOCK = 0 END BLOCK = 9197 TEST TYPE = SEEK LOOP COUNT = 100 ERROR MESSAGE DISPLAY - There are two basic types of error message formats used. One is for messages displayed during the DMA TEST, the other is for all other tests. The following is a discription of the two formats: +ERROR MSG: SLOT/BLOCK#/ERROR-STATUS CODE +ERROR MSG: BLOCK#/ERROR-STATUS CODE The block number may be displayed in either hex, octal, or dec, corresponding to how the PARM TYPE is set from the hdtest main menu. (Use the 'F2' functions key to select PARM TYPE). The following is a list of all the possible error messages that will be displayed by the diagnostics tester: WRT ERROR HARD ERR SOFT ERR DATA MISS PSOFT ERR DMA ERR NOT SAVED NOT RSTRD HDTEST OPERATING SYSTEM OVERVIEW The principle theory of operation behind the HDTEST operating system is to create a standardized environment for diagnostics pro- cessing on all devices. HDTEST can = XX BLKS/TRACK = XX BYTES/BLOCK = XXX INTERLEAVE = XX WPRECMP CYL = XXX The only device currently supported by HDTEST is the rigid hard disc, with either the Xebec or Western Digital controllers. Slots A through E on the mother board may be selected for device communication. A variety of preprogrammed disc drive model types, (see list next page), are available which, when selected, will automatically initialize the number of cylinders, number of heads, reduced write current cylinder, and the write precompensation cylinder. In order to select a drive environment that does not match any of the types the drive type list, toggle* the 'DRIVE TYPE' window until 'OTHER' is displayed. When the cursor is positioned at the bottom of the lower right hand side of the main menu, next to the '>' command prompt, then type the command 'init' followed by a carriage return. In the upper portion of the main menu the following information will be prompted for: UNIT NUMBER = X STEP RATE = XX AD be divided into three major groups or processes. 1.) Single command entry mode allows the operator to address a given device and execute any command acceptable to the controller of that device and receive an appropriate go no-go response. A device command falls into one of three categories, non-data command, read-data command and write-data command. A device command may be as simple as a byte sequence to a controller or as complex as a complete series of tests for a given process. In single command entry mode one, and only one, command may be executed at a time. 2.) Command history mode 'chains' together several commands, no more than 100, for rapid sequential execution. All error trapping and error reporting facilities are op- erational in this mode. Note: errors are not saved in any type of storage or file and will only be reported at time of occurance, the wait function of the error trap should be used if operator wis DRESS = X BLOCK COUNT = X INTERLEAVE = X BLK / TRACK = XX LOOP COUNT = X # OF CYLS = XXX # OF HEADS = XX WPRECMP CYL = XXX *toggle is defined as the action of hitting any key on the keyboard, (except the 'UP cursor key', 'DOWN cursor key', 'LEFT cursor key', 'F11', 'F10', 'execute', 'cancel/del' keys), to change the message appearing opposite the positioned prompt. If you wish to display the previous message then hit the 'LEFT cursor key'. Simply hand set the desired values to each of the above parameters, corresponding to the rigid disc drive to be tested, then hit the 'F11' key. The new drive environment values should appear in the device select window of the main menu and the cursor positioned next to the '>' command prompt. Drive Type options list: A10 - Seagate 10 Megabyte (ST412) B05 - Miniscribe 5 Megabyte B10 - Miniscribe 10 Megabyte C20 - Ampex 20 Megabyte G25 - Atasi 25 Megabyte H25 - Evotec 25 Megabyte I20 - Disctron 20 Megabyte J20 - CDC 20 Megabyte J30 - @J( @/( ug(/< N^NuN CDC 30 Megabyte K40 - Maxtor 40 Megabyte K50 - Maxtor 50 Megabyte Z05 - Seagate 5 Megabyte (ST506) OTHER - (Use the 'init' command to select device) 0`( n gb`r/< N^NuN N^NuN N^NuN t /. N^NuN N^NuN gR(m (@+L `( - N^NuN fZ(m gN - oD+L h0< N^NuN `( 9 @B( N^NuN l2 N^NuN N^NuN N^NuN fHHUN N^NuN N^Nu N^Nu N^NuN N^Nu N^Nu N^Nu W"( W2( Nu0< &N@NuNuNu N^NuN f( < N^NuN *@(n N^NuN `BHT HT . HT . N^Nu Nu0< l, < NuN@e l, < l, < Nu0< B@H@ H@`6 |N^NuN 1XNV >4&| fJJSf BTRy NqBy f\/< >4fJBTRy NqBy >4f* BTRy NqBy JTf8 fbHU/< HU/< fJJSf fNJRf N^NuN 1XNV fJJRf fJJRf N^NuN 1XNV fJJRf fJJRf N^NuN 1XNV g&/< N^NuN 1XNV N^NuN 1XNV `\0. ;R @=P N^NuN 1XNV >4&| BTRy NqBR >x`. >4f*BTRy NqBR `bBTRy NqBRJTf N^NuN 1XNV N^NuN 1XNV N^NuN 1XNV N^NuN 1XNV >|/9 >@/< >8/9 N^NuN 1XNV N^NuN 1XNV ;R @=P N^NuN 1XNV `\0. ;X @=P ;X @=P N^NuN 1XNV `\0. ;x @=P ;x @=P N^NuN 1XNV gtJy fP0. HU/< BRJy fNJRf N^NuN 1XNV `n n fVJy N^Nu 1XNV >4Jy >< 9 `6/< yG g N^NuN 1XNV g8/< BSJy BSJy BSJy #XBS/< $zBS/< N^NuN 1XNV `f S fNJRf `| S fNJRf N^NuN 1XNV fNJRf >4Jy N^NuN 1XNV x(H` x(HB. *g*B n"" Lgnn xgd` xg:S n&H`J/ l p0` x&H DN^NuN 1XNV N^NuN 1XNV N^Nu H@`6 N^Nu HABA N^NuNV B@H@ B@H@` N^Nu@(#)diag_copyrt.s 1.4 @(#)meminit.s 1.3 type %d read-modify-write error (loc %x) @(#)Fortune Systems Diagnostic Release 4.0 (1.7) Memory test terminated. Press reset button to continue. Fortune Systems Memory Diagnostic Version %s %s Program/data reside in ram between locations 0x%x and 0x%x. Memory test interrupted. Do you want to terminate this test Test Slot 1 memory from 0 to 4000(hex) After reset use configuration menu key (F7) to enter fd02/memlow Upon receiving the boot prompt ':' enter fd02/memlow memory test start location end location silent error reporting pause on errors check parity use quick test only The following range of memory locations will now be tested: 1XNV fX/< f&J. vg8/< N^Nu 1XNV `Z . =Rf to start test or to re-enter parameters... pass %d test %d loc %X wrote %x read %x xor %x type %c ERROR: pint2 flipflop appears stuck (set) ERROR: pint2 flipflop not set when expected ERROR: no parity interrupt: addr = 0x%X ERROR: parity addr latch error: addr = 0x%X, latch = 0x%X %s pass %d: pass errors = %d, cum. errors = %d interrupted error addresses: and = %X or = %X cumulative parity errors = %d; errors that occured: unexpected parity interrupt expected interrupt did not occur addresses of above errors: and = %X, or = %X pint2 flipflop was not clear when expected pint2 flipflop was not set when expected %d h/w parity latch errors: and = %X, or = %X %d refresh time-outs Refresh timeout error @(#)memtst.c 1.4 error at loc %X ( N^NuN sLNV ,fH/. N^NuN sLNV N^NuN sLNV fJJSf BTRy NqBy ,f\/< fJBTRy NqBy BTRy NqBy PJTf8 ,fbHU/< HU/< fJJSf N^NuN sLNV BTRy NqBR data = %X expected = %X) @(#)version.c 1.5 <&1.5 9/8/83 01:41:07 @(#)parint.c 1.2 unexpected parity error: H/W addr = %X, cum. parity error = %d pint2 is also active @(#)diag_printf.c 1.5 (bootprt) (null) @(#)diag_param.c 2.5 %s (0x%X)? %s (%D)? that function key not recognized here. non-numerical entry. @(#)diag_yesno.c 2.4 %s (%s)? Please answer yes or no? @(#)diag_atoi.c 1.2 @(#)diag_gets.c 2.3 DEL @(#)diag_csavret.s 1.3 @(#)diag_clear.s 1.3 @(#)diag_setjmp.s 1.2 @(#)diag_initcrt.c 1.2 f*BTRy NqBR `bBTRy NqBRJTf H`, N^NuN sLNV N^NuN sLNV N^NuN sLNV N^NuN sLNV g$/9 N^NuN sLNV N^NuN sLNV `6/< yG g N^Nu sLNV ~COPYRIGHT 1982 FORTUNE SYSTEMS CORPORATION. DISCLOSURE TO OTHERS PROHIBITED. FOR TERMS OF USE REFER TO LICENSE AGREEMENT. N^.y Ns o sLNV ,BTBy ttBR/< g BTJRg ``BT/< nNuN sLNV $gF/ f2/< p"C$D&E& p"C$D&E" h>BUJy gp/< p"C$D&E& p"C$D&E" BUJy g6/< crBU/< p"C$D&E& p"C$D&E" p"C$D&E& p"C$D&E" p"C$D&E& p"C$D&E" p"C$D&E& p"C$D&E" a2/< p"C$D&E& p"C$D&E" p"C$D&E& gpJy ,fH/. BRJy fNJRf N^NuN sLNV `: n g . N^NuN sLNV `f n fNJRf gtJy ,fL0. BRJy fNJRf N^NuN sLNV p"C$D&E" p"C$D&E& p"C$D&E" p"C$D&E& p"C$D&E" p"C$D&E& p"C$D&E" BU/< d>BU$ d>BU$ p"C$D&E& fjBUH p"C$D&E" d>BUL N^NuN sLNV `f S fNJRf `| S fNJRf N^NuN sLNV `$ R `8 n g . N^NuN sLNV fJJRf fJJRf N^NuN sLNV N^NuN sLNV g&/< N^NuN sLNV g&/< N^NuN sLNV N^NuN sLNV `\0. |J @=P |J @=P N^NuN sLNV `\0. |j @=P |j @=P N^NuN sLNV N^NuN sLNV fNJRf fNJRf N^NuN sLNV N^NuN sLNV fJJRf fJJRf N^NuN sLNV N^NuN sLNV `h . fNJRf gtJy ,fP0. HU/< BRJy fNJRf N^NuN sLNV `\0. @=P @=P N^NuN sLNV `\0. @=P @=P N^NuN sLNV N^NuN sLNV N^NuN sLNV `n n fVJy N^NuN sLNV `\0. @=P @=P N^NuN sLNV `\0. DN^NuN sLNV N^NuN sLNV N^Nu sLNV ~nfX/< ~nf&J. vg8/< N^Nu sLNV `Z . f&J. vg"/< N^Nu sLNV @=P @=P N^Nu sLNV N^NuN sLNV x(H` x(HB. *g*B n"" Lgnn xgd` xg:S n&H`J/ l p0` x&H 9o$ . `< . 9n<". N^NuN sLNV P(@N ^gT`X 2~{` <`8S N^NuN sLNV N^Nu NuNuNu Nu o sLNV N^Nu _ `H o R@NuB R@NuB R@Nu H@`6 N^Nu HABA N^NuNV B@H@ B@H@` N^Nu@(#)diag_copyrt.s 1.4 @(#)meminit.s 1.1 type %d read-modify-write error (loc %x) @(#)Fortune Systems Diagnostic Release 4.0 (1.3) Fortune Systems Low-Memory Diagnostic Version %s %s Memory test interrupted. Do you want to terminate this test Discontinue low-memory testing Upon receiving the boot prompt ':' enter the desired test or reset. silent error reporting pause on errors The following memory locations on the slot 1 memory card will now be tested: s ~COPYRIGHT 1982 FORTUNE SYSTEMS CORPORATION. DISCLOSURE TO OTHERS PROHIBITED. FOR TERMS OF USE REFER TO LICENSE AGREEMENT. .*.| N^.y .*NuH Ns o Nu o N@Nu o Nu o N@Nu .b$| 8X @ 8\ @ 8( @B 8, @B gD/. tart loc = %X end loc = %X # bytes = %X hit to start test or to re-enter parameters... pass %d test %d loc %X wrote %x read %x xor %x type %c ERROR: pint2 flipflop appears stuck (set) ERROR: pint2 flipflop not set when expected ERROR: no parity interrupt: addr = 0x%X ERROR: parity addr latch error: addr = 0x%X, latch = 0x%X %s pass %d: pass errors = %d, cum. errors = %d interrupted error addresses: and = %X or = %X cumulative parity errors = %d; errors that occured: unexpected parity interrupt expected interrupt did not occur addresses of above errors: and = %X, or = %X pint2 flipflop was not clear when expected pint2 flipflop was not set when expected %d h/w parity latch errors: and = %X, or = %X %d refresh time-outs Refresh timeout error @(#)memtst.c 1.2 @ . .r"@" g* . 8( @R .z`h 8, @R S"S" .r"@" .r"@" fX/< .r"@" error at loc %X (data = %X) error at loc %X (data = %X) error at loc %X (data = %X expected = %X) @(#)version.c 1.1 9/8/83 14:03:53 @(#)parint.c 1.1 unexpected parity error: H/W addr = %X, cum. parity error = %d pint2 is also active @(#)diag_printf.c 1.5 (bootprt) (null) @(#)diag_param.c 2.5 %s (0x%X)? %s (%D)? that function key not recognized here. non-numerical entry. @(#)diag_yesno.c 2.4 %s (%s)? Please answer yes or no? @(#)diag_atoi.c 1.2 @(#)diag_gets.c 2.3 DEL @(#)diag_csavret.s 1.3 @(#)diag_clear.s 1.3 @(#)diag_setjmp.s 1.2 @(#)diag_initcrt.c 1.2 .r"@" gN/9 fV/< 8HgxB9 8 gjJ fb/9 8 gd gn/9 x(HB. *g*B n"" Lgnn xgd` xg:S n&H`J/ l p0` x&H DN^NuN N^NuN N^Nu 8xJn 6VfX/< 6Vf&J. vg8/< g$/9 8$/9 f$ . 8( @J 8, @J gR . 8, @/ 8( @/ gR . 8\ @/ 8X @/ `2 n N^NuN 8L$< g" . .v @ JSf@ 8X @ 8\ @ N^NuN N^NuN `L/< yG g N^Nu 8xJn `Z . f&J. vg"/< N^Nu 9o$ . `< . 9n<". N^NuN P(@N ^gT`X N^NuN 8H`8 . N^NuN .b A"< N^NuN .b A"< N^NuN .d A"< N^NuN N^NuN N^NuN N^NuN N^NuN f: . .~ @/ N^NuN 8L$< .b @ .r"@" N^NuN x(H` 2~{` 7$`8S N^NuN N^Nu NuNuNu Nu o N^NuNV H@`6 N^Nu HABA N^NuNV B@H@ B@H@` N^Nu@(#)diag_copyrt.s 1.4 @(#)mmuinit.s 1.4 @(#)Fortune System Diagnostic Release 3.0 (1.11) TDXS ERROR: expected bus error did not occur on IODE test. ERROR: bus error did not prevent IODE. ERROR: software doorbell stuck. Can't test IODE. MMU test terminated. Press reset button to continue. Fortune Systems Memory Management Unit Diagnostic Version %s %s Please verify last ram location pause on error hit ESC to contin ~COPYRIGHT 1982 FORTUNE SYSTEMS CORPORATION. DISCLOSURE TO OTHERS PROHIBITED. FOR TERMS OF USE REFER TO LICENSE AGREEMENT. N^NuN N^NuN N^NuN N^NuN N^NuN N^NuN ue after errors. starting %c segment (%X) - user mode %c segment mmu register = %X hit escape to continue... checking write to read-only segment: ERROR - no trap on write to read-only seg (%c seg) ERROR: trap ocurred (%c seg r/o), but write was not suppressed. trap ocurred as expected ERROR: can't restore location %X checking user mode access of upper memory: ERROR: user mode access of upper memory not suppressed (%c seg). trap ocurred as expected checking IODE supression trap ocurred as expected. ---mmu[%c%s] set = %X, limit = %X, base = %X (user) MMU test interrupted terminate test continuing. %c seg %sPARITY ERROR: virtual (%X); physical (%X) = %X (user) expected trap: v_addr = %X p_addr = %X (parity trap) [%c seg] v_addr=%X v_data=%X p_addr=%X p_data=%X no mem at %X - parity trap occured mmu pass %D: total cumulative errors = %D IODE errors: %D no bus error, %D no iode supression, %D stuck s/w int latch user mode errs N^NuN N^NuN N^NuN g @J D @J : %D mapping, %D no trap on upper memory access %c seg errs: %D mapping, %D no r/o trap, %D r/o trap+write (virt addr: and %X, or %X)(phys: and %X, or %X) filling memory from %X to %X: checking data: bad data %X at loc %X no trap trap %c seg ERROR: virtual (%X) = %X; physical (%X) = %X hit to continue... unexpected bus error - Hit DEL unexpected parity error, pc = 0x%X, access addr = 0x%x pint2 is also active ERROR: unexpected bus error while setting doorbell @(#)version.c 2.2 9/29/82 16:12:46 @(#)diag_printf.c 1.5 (bootprt) (null) @(#)diag_param.c 2.5 %s (0x%X)? %s (%D)? that function key not recognized here. non-numerical entry. @(#)diag_yesno.c 2.4 %s (%s)? Please answer yes or no? @(#)diag_atoi.c 1.2 @(#)diag_gets.c 2.3 DEL @(#)diag_csavret.s 1.3 @(#)diag_setjmp.s 1.2 @(#)diag_initcrt.c 1.2 N^NuN g @B g @J N^NuN N^NuN N^NuN N^NuN BEBG N^NuN N^Nu 0(APH AP-@ z n 0(AXH AX-@ 0(AHH AH-@ 0(ALH AL-@ 0(ATH AT-@ g AJ h A# h A# D @J 0(A\H A\-@ 0(A@H A@-@ 0(ADH AD-@ N^NuN D @B BFBG N^Nu AH n 0(AHH AH-@ BhAH n 0(AHH AH-@ AL n 0(ALH AL-@ BhAL n 0(ALH AL-@ AT n 0(ATH AT-@ BhAT n 0(ATH AT-@ A@ n 0(A@H A@-@ BhA@ n 0(A@H A@-@ AD n 0(ADH AD-@ BhAD n 0(ADH AD-@ BhA\ n 0(A\H A\-@ @A-@ @A-@ @A-@ @A-@ A\ n 0(A\H A\-@ ALJ9 `A-@ BhALp BhALp ` `A-@ BhALp BhALp ` BhAL n `A-@ BhALp!` ( n BhALp"` `A-@ BhALp!` BhALp BhALB@` N^NuN AH . H @0 AH-@ BhAH . H @0 AH-@ AL . L @0 AL-@ BhAL . L @0 AL-@ AT . T @0 AT-@ BhAT . T @0 AT-@ A@ . @ @0 A@-@ BhA@ . @ @0 A@-@ AD . D @0 AD-@ BhALp"` BhAL n `A-@ BhALp#` BhALp$` `A-@ BhALp#` BhALp$` `A-@ `A-@ BhALp `A-@ `A-@ BhALp BhAD . D @0 AD-@ A\ . \ @0 A\-@ BhALp BhALp BhALp BhALp `P-@ `P-@ BhALp `P-@ `P-@ BhALp BhALp BhA\ . \ @0 A\-@ BhALp BhALp BhALp BhALp BhALp `P-@ BhALp `P-@ BhALp @A-@ @A-@ ALJ9 `A-@ BhALp BhALp ` `A-@ BhALp BhALp ` BhAL n BhALp!` ( n BhALp BhALp BhALB@` N^NuN N^NuN BhAP n AP n AT n BhAT n 0(APH AP-@ BhAP n AP n 0(APH AP-@ AT n BhAT n 0(APH AP-@ BhALp"` BhALp!` BhALp"` BhAL n BhALp#` BhALp$` BhALp#` BhALp$` `A-@ BhALp `A-@ BhAP n AP n 0(APH AP-@ N^NuN A@ n AD=| @JPf @JPg BhA@ n BhADp 0(ADH 0(A@H A@-@ AD-@ 0(A@H A@-@ N^NuN 0(`P n BhALp BhALB@` N^Nu AD n A@ . @JPg @=P @=P @0. 0(ADH BhAD` 0(A@H BhA@ . AD-@ BhALp 0(A@H BhA@` A@-@ BhALp 0(APH AP-@ BhALp N^Nu BhAP n AP n AT n Np n BhAT n 0(APH AP-@ BhAP n AP n Np n 0(APH AP-@ @JPg 0(ADH BhAD` 0(A@H BhA@ . AD-@ 0(A@H BhA@` A@-@ N^NuN 0(ADH BhAD` 0(A@H BhA@ . AD-@ BhALp 0(A@H BhA@` A@-@ BhALp 0(APH AP-@ BhALp N^NuN *@ . (@>. N^NuN *@ . N^NuN AD n A@-| @JPg N^NuN AL . AD n A@-| 0(ADH BhAD` 0(A@H BhA@ . AD-@ BhALp 0(A@H BhA@` A@-@ BhALp 0(APH AP-@ BhALp @JPg BhALp > @0 BhALp `P-@ 0(ADH BhAD` 0(A@H BhALp BhA@ . AD-@ BhALp 0(A@H BhA@` A@-@ BhALp AP-@ BhALp BhALp BhALp N^Nu 0(AXH AX-@ AX n 0(AXH 0(AXH AX-@ BhAXp BhAX . BP n AD n A@-| 0(ADH BhAD` 0(A@H BhA\p 0(APH AP-@ BhA\p BhA\p BhA\p ZZ n BP n AD n A@-| BhAD n BhA@ n BhA\p BhAD n BhA@ n BhA\p BhA\p BhA@ . AD-@ 0(A@H BhA@` A@-@ 0(APH AP-@ 0(AXH N^Nu A\ n @@A-| ZZ . BP n AD n A@-| PZZg 1|ZZ BhAD n BhA@ n BhA\p BhA\p 0(ADH BhAD` 0(A@H BhA\ n 0(ADH BhAD` 0(A@H BhA\ n BhA@ . AD-@ 0(A@H BhA@` A@-@ BhA\p 0(APH AP-@ BhA\p BhA\p 1|ZZ BhA\p BP n AD n A@-| BhAD n BhA@ n BhA\p BhA@ . AD-@ BhA\p 0(A@H BhA@` A@-@ BhA\p 0(APH AP-@ BhA\p BhA\p BP n AD n A@-| (@AH @A n BhA\p 0(ADH BhAD` 0(A@H BhA\ n BhA@ . AD-@ 0(A@H BhA@` BhAD n BhA@ n BhA\p BhA\p 0(ADH BhAD` 0(A@H BhA\ n BhA@ . AD-@ 0(A@H BhA@` A@-@ BhA\p 0(APH AP-@ BhA\p BhA\p BhA\p ` BhA\B@` N^NuN A\-| 3@A-| BP n BhA\p AD n A@ n BhA\p 0(ADH BhAD` 0(A@H BhA\ n BhA@ . AD-@ BhA\p 0(A@H BhA@` A@-@ BhA\p 0(APH AP-@ BhA\p BhA\p AD n A@ n BhA\p 0(ADH BhAD` 0(A@H BhA\ n BhA@ . AD-@ BhA\p BhA\p BhA\p BhA\p BhA\p BhA\p BhA\p BhA\p AD n A@ . 0(ADH BhAD` 0(A@H BhA\ n F n BhA@ . AD-@ 0(A@H BhA@` A@-@ BhA\p 0(APH AP-@ BhA\p BhA\p BhA\B@` N^Nu @"@$@&@(@*@,@ < 0 [arg1] [arg2]; ... Use 'HELP'.....to reprint this summary Use 'DEL rect test operation. Are you using the special test fixture, yes or no PIO's under test= Tests to be run= Repeat count= %d Will Loop on first error occurence Looping on selected test(s) and slot(s) until the first error occurrs Looping on selected test(s) and slot(s) regardless of error occurrences Loop mode disabled Total errors= %d Memory Page = %d Pause on Error Selected Pause on Error Not Selected Parallel Port Testing has been enabled. The Special Test Fixture must be installed. Parallel Port Testing has been enabled. The Special Test Fixture will not be used. Parallel Port Testing is disabled Slot %c will be tested abcde ABCDE invalid slot letter: %c invalid loop argument: %c no pause argument expected: %c Testing has been terminated. Slot number: %c Test number: %x Pass number: %d Errors: %d Passed Slot number: %c Test number: %x Pass number: %d Failed stat= %d adr= %x exp= %x act= %x page= %d errs= %d stat= %d adr= %x exp= %x act= % '......to terminate testing after completion of the currently executing test a(ddr).........arg(s) are a list of option slots to test 'abcde' if no arg, selects slot 'B' to be tested c(ount)........arg1 is the number of times to repeat test d(isplay)......prints all currently selected options e(nable).......parallel port testing -e(nable)......disables parallel port testing g(o)...........executes selected tests l(oop).........if arg1 is 'e', sets test to loop on first error 'a' sets selected test(s) to loop till killed 'f' arg sets selected test(s) to loop till first error -l(oop)........turns off loop mode p(ause)........on any error untill the space bar is pressed -p(ause).......turns off pause mode q(uit).........exits to boot prompt ':' t(est).........arg(s) select specific tests to be run use arg-arg for a range of tests to be run if no arg, prints description of all tests and x page= %d pass= %d errs= %d Slot number: %c Test number: %x Pass number: %d Failed stat= %d adr= %x exp= %x act= %x page= %d errs= %d 123456789abcdef invalid test number: %c Try 1-%x 123456789abcdef invalid test number: %c Try 1-%x out-of-order arguments: %x %x Try again a '-' command requires an 'l' argument invalid argument: -%c @(#)pio_t11.c 1.1 @(#)pio_t12.c 1.1 @(#)pio_t13.c 1.1 @(#)pio_t14.c 1.1 @(#)pio_t15.c 1.1 @(#)pio_t16.c 1.1 @(#)pio_t17.c 1.1 @(#)pio_t18.c 1.1 @(#)pio_t19.c 1.1 @(#)pio_t21.c 1.1 @(#)pio_t22.c 1.1 NpNr @(#)pio_t23.c 1.1 @(#)pio_t24.c 1.1 @(#)pio_t25.c 1.1 @(#)pio_t26.c 1.1 @(#)pioarb.s 1.1 @(#)pioarb1.s 1.1 @(#)piomem.s 1.1 @(#)piomem1.s 1.1 @(#)pioself.s 1.2 @(#)intrupt.s 1.1 @(#)intrupt1.s 1.1 @(#)pioint.s 1.1 @(#)pioint1.s 1.1 @(#)pioint2.s 1.1 @(#)pioint3.s 1.1 @(#)rtcint.s 1.1 @(#)ports.s 1.1 @(#)portloop.s 1.1 @(#)pintrupt.s 1.1 (@+L `( - N^NuN fZ(m gN - oD+L N^NuN N^NuN fHHUN N^Nu0< W"( W2( Nu0< &N@NuNuNu N^NuN f( < (@ 9 @(#)pro.s 1.1 @(#)pro1.s 1.1 @(#)pro2.s 1.1 @(#)pro3.s 1.1 @(#)asm21.s 1.1 @(#)initmem.s 1.1 @(#)printf.c 1.1 (null) @(#)diag_yesno.c 2.4 %s (%s)? Please answer yes or no? @(#)diag_gets.c 2.3 DEL @(#)diag_csavret.s 1.3 @(#)diag_setjmp.s 1.2 @(#)diag_initcrt.c 1.2 p S N^NuN N^NuN g`-M N^Nu t /. N^NuN N^Nu 9 dNu0< NuN@e Nu0< @(#)Fortune Systems Diagnostic Release 3.0 (1.2) h*B(| h~ z pP-@ g6/< *@/. N^Nu B@H@ B@H@` N^NuNV HABA N^NuN 9nP" N^NuN N^NuN gR(m