Chapter 2 - Hardware Description

2.0 Central Processing Unit (CPU)

The MC6802 microcomputer chip is the CPU of the MEK6802D3 computer board. The MC6802 is a 6800 microprocessor with additional features; a clock oscillator circuit and 128 bytes of RAM. This powerful microcomputer chip contains an arithmetic logic unit (ALU), various registers, and control logic. It has a set of 72 different instructions that include binary and decimal arithmetic logic, shift, rotate, fetch, store, branch interrupt, and stack manipulation. For more detailed information, see the MC6802 data sheet in the appendix. with coded instructions from memory, the MC6802 controls and manipulates address, data, and control information within the system. Thus, the MC6802 is the heart of the MEK6802D3 computer' system and interfaces with the rest of the components on the board„as illustrated in the system block diagram, Figure 2.0.1.

SYSTEM BUS: There are two buses on the computer card; the internal bus that interconnects components on the card and the external or system bus that connects the MEK6802D3 card with the system expansion cards.

The internal bus contains the following signals:

1. 16 address lines: A0 - A15
2. 8 data lines: D0 - D7
3. 9 control lines
   1. E - ENABLE - This signal is the system clock. A standard 3.579545 MHz crystal is used by the processor to generate the 894.8 KHz system clock.
   2. R/W - Read/Write - This is the read­write control line. Its logic state determines the direction of data (into or out of) a selected chip.
   3. VMA - Valid Memory Address - This control signal indicates that a valid address is on the address bus.
   4. MR - Memory Ready - This control signal can cause the E signal to be stretched. when MR is high, E will be in normal operation. when MR is low, E may be stretched an integral multiple of half periods, thus allowing interface to slow devices.
   5. RESET - this line is used to reset and start the MPU.
   6. BA - Bus Available - When this signal is active, the MC6802 is stopped and the address bus is avaiïable for external devices.
   7. HALT - When this signal is active, all activity of the MC6802 wi11 be halted.
   8. IRQ - Interrupt Request - This signal requests that an interrupt sequence be generated within the MC6802.
   9. NMI - Non-Maskable Interrupt - This signal is similar to IRQ except that the interrupt mask bit in the condition code register cannot prevent this interrupt from being executed.

A detailed description of these control signals is given in the appendix. The timing relationship of E, R/W, and VMA with respect to address and data signals is shown ín the following figure.

2.1 Memory and Address Decode Logic

As mentioned earlier, the MEK6802D3 has two types of memory devices; RAM and ROM.

RAM: The on board RAM consists of two MGM6810's that contain 128 bytes each of static storage and 128 bytes located within the MC6802 MPU itself. This random access memory is used for the temporary storage of the user program and variable data.

The actual location of RAM is determined by the address combination connected to the memory component chip selects. As noted earlier in Figure 1.1.1, the first 128 bytes are located from hex address $0000 to $007F. This memory is contained inside the MPU chip and, as illustrated in the address map of Table 2.1.1, does not require any address decoding. Address lines A0 - A6 select one byte out of the possible 128 bytes. If for some reason the user does not want to use the MPU RAM, it can be disabled by placing a jumper in E7; see system schematic (Appendix 3). A jumper in E7 will ground the RAM enable (RE) input and disable the memory from the bus.

The remaining 256 bytes of RAM are obtained with MCM6810 memory chips. Their address locations are determined by the address combination given in Table 2.1.1. The MCM6810 has six chip selects with only three being used for decode; CSG, CS1, and CS2. One MCM6810 (device U30) has the chip selects set to respond to hex address $0080 to $007F. However, as noted in Table 1.1.1 and 2.1.1, the address selection can be moved to hex address $8180 to $81FF. This can be accomplished by removing jumpers E4 and E5 and inserting jumpers in E3 and E6.

The other MCM6810 is located at $8100 to $817F. This 128 byte block of RAM is employed as stack memory for the D3BUG monitor and should not be used for general purpose storage of user programs.

ROM: The MEK6802D3 monitor (D3BUG) is contained in the 2K bytes of ROM of the MC6846. In addition to the ROM, the MC6846 has a bidirectional I/0 port and a timer­counter function. The ROM section of the MC6846 is selected with address select lines MROM and MIO. with these select lines, the ROM is enabled for hex address space $F800 to $FFFF as given in Table 2.1.1. A detailed description of the software is given in Chapter 4 along with an assembly listing (Appendix 1). It was mentioned in Chapter 1 that to enhance the computer board with additional support boards, would require the D3BUG software to be expanded by another 2K bytes. This expansion ROM (MCM68316 - U29) is located in hex address space $F000 to $F7FF. The features of this ROM are given in Chapter 3 and a detailed description and the binary code listing are given in the MEK68R2M manual.

ADDRESS SPACE DECODE: The address space of the computer is fully decoded. There are two 74LS138's (one of eight decoder) that decode address lines A7 through A9 and A13 through A15; see system schematic, (Appendix 3). Table 2.1.2 lists the decoded address space. The three most significant address lines, A13 through A15 are decoded into eight 8K block select lines ADRO-1 thru ADRE-F. For hex address space $0000 to $1FFF, the decoded select output ADRO-1 will be a logic "0". The other decoded lines will be a logic "1". For address space $2000 to $3FFF, select line ADR2-3 will be a logic "0" and so on for the remainder of the select lines.

Address lines A7 through A9 generate the eight decoded select lines DCD0 thru DCD7. Note however from Table 2.1.2 that the decode range for the most significant hex digit is not contiguous. That is, DCD0 is a logic "G" for the following address ranges:

• $0000 to $007F
• $2000 to $207F
• $4000 to $407F
• $6000 to $607F
• $8000 to $807F
• $A000 to $A07F
• $C000 to $C07F
• $E000 to $E07F

The reason for this peculiar address range select is that the enable inputs of the 1 to 8 decoder U11 are driven by address lines A10, A11, and A12.

Some of these decoded outputs are logically combined with other address lines or some of the other decode lines, such as ADR8-9 to generate the following decode select lines:

• I/O1 - $8000 to $807F
• I/O2 - $8080 to $80FF
• MIO - $8080 to $808F
• MROM - $F800 to $FFFF

The I/O1 and I/O2 lines go to the system bus and define the peripheral I/0 address range for an expanded system. See Chapter 3 for additional information on these two signals. The decoded address lines are a1so used for the decode of RAM and ROM.

Since the above mentioned decoded address space is used for the control of the on board internal data bus (addresses from $0100 to $1FFF are to be included in this address space), this memory space cannot be used off board in an expanded system. To insure this, the bidirectional data buffers (U2 and U3) are forced into a data out mode by signal RDE. The above select lines plus the R/W control and E clock are logically combined through gate U27 to insure that RDE wi11 always force the data buffers into an output mode.If the $0000 to $1FFF address space must be utilized in an expanded system, then the following change must be made to the board:

• Remove E9
• Insert E10
• Insert E7
• Change the address of U30 from $0080 - $00FF to $8180 - $81FF by changing the jumpers as noted earlier.

For complete jumper detaiïs, see Chapter 3.

2.2 I/O

KEYBOARD/DISPLAY: The keyboard and display connect to the on board bus through U8, the peripherial interface adapter (PIA) MC6821. A scanning technique is used on both the keyboad and display to reduce hardware, power, and cost. Since the operation of this circuitry is controlled by the monitor program, refer to the software description in sections 4.2, 4.3, 4.4 and the system schematic (Appendix 3) to follow the description of the keyboard/display operation.

DISPLAY: The scanning procedure uses PIA lines PB0 through PB7 and the seven segment pattern to be displayed is controlled by PIA lines PAO through PA6. The display routine called PUT (detailed in section 4.2) controls the display logic in the following manner; first the PUT routine determines which of the eight displays will exhibit the desired data by taking one of the PIA PB lines high. For explanation purposes assume PB7 goes high. Next the PUT routine sends the desired seven segement data from DISBUF to the eight displays, U18 through U25. Since PB7 is high, the selected segments of U18 will be turned on. PB0 through PB6 remain low preventing U19 through U25 from displaying data. Then the PUT routine delays for one millisecond. During this one millisecond, U18 will be turned on. Next the PUT routine will select the data pattern to be displayed on U19, which is the next display and PIA bit PB6 will be set and PB7 cleared. This sequence continues until the right most digit, U25, has been selected. Next the program returns to display U18 and the sequence repeats itself. This sequence or refresh rate is sufficient to make the displays appear to be on continuously.

Note that (system schematic, Appendix 3) the PIA PB0 through PB7 and PA0 through PA6 are buffered. The buffers U17, U14, U15, U33 and U34 are necessary to supply the high current required by the LED displays.

KEYPAD: The keypad has 25 keys that are electrically arranged in four columns by six rows. The reset key (RS) is not decoded and is not part of the row/column matrix; see Appendix 3, sheet 3. Note that the rows of the key matrix are driven by the seiect display driver buffers U19, U33, and U34. Thus as the PUT routing sequentially selects the displays U20 through U25, the corresponding rows of the key matrix will be selected. The select state is a logic "0" or ground. The four columns of the matrix are connected to NAND gate U26B and the four to one demultiplexer, U28A.

When one of the keys in the matrix is depressed, the output of gate U27B will be forced to a logic "1" when the row buffer that the key is attached to goes low. The logic "1" from U27B causes the PIA U8 to set an 'IWT interrupt, see section 4.3 for a description of the Keypad/Decode routine when the keypad interrupt is acknowledged, all of the displays are blanked by storing 90 to the segment or data lines of the displays. Next a routine is used to determine the column of the key depressed. This routine sequences PIA lines PB6 and PB7. when the output of the four to one demultiplexer goes low, the PIA PA7 line is driven low. This low on PA7 will tell the routine which co1umn was seïected by the binary state of the PB6 and PB7 lines.

Next a row find routine is executed. This routine sequentially drives each one of the PB0 through PB5 lines high until the active row is found. There is a key table that corresponds to the key matrix, so when the row and column address of the depressed key is found, the key table can be accessed and the value of the key loaded into che A accumulator. The reset button does not require decoding because it is tied to the power up reset logic which drives the RESET input of the 6802 directly.

SK1 SOCKET: The MEK6802D3 board has one I/0 port available for the user other than the D3 I/0 system expansion bus. A 16 pin socket SK1 allows the user to interface to the timer and parallel port of the MC6846. The parallel bidirectional I/0 port has functional operational characterigtics similar to the B port on the MC6821 PIA. These include 8 bidirectional data lines, P0 through P7, and two handshake lines, CP1 and CP2. The control and operation of these lines are completely software programmable. The PIA timer address space is from $8080 to $8087 see Figure 1.1.1.

The timer­counter port is a 16 bit binary counter which under software control may be programmed to count events or measure frequencies and time intervaìs. It can also be used for square wave generation, single pulses of controlled duration, and gated signal interrupts may be generated from a number of conditions selectable by software. The CTO (counter timer output) signal is used by D3BUG software to generate a NMI during single step operation.